A new method of forming a thin single-crystal silicon diaphragmusing merged epitaxial lateral overgrowth for sensor applications

Merged epitaxial lateral overgrowth (MELO) of silicon was combined with an SiO₂ etch stop to form a 9-μm-thick and 250-μm×1000-μm single-crystal Si membrane for micromechanical sensors. When epitaxial lateral overgrowth (ELO) silicon merges on SiO₂ islands, it forms a local silicon-on-insulator (SOI) film of moderate doping concentration. The SiO₂ island then acts as a near-perfect etch top in a KOH- or ethylenediamine-based solution. The silicon diaphragm thickness over a 3-in wafer has a standard deviation of 0.5 μm and is precisely controlled by the epitaxial silicon growth rate (≈0.1 μm/min) rather than by conventional etching techniques. Diodes fabricated in the substrate and over MELO regions have nearly identical reverse-bias currents, indicating good quality silicon in the membrane     

Cutoff frequency and propagation delay time of 1.5-nm gate oxideCMOS

The high-frequency AC characteristics of 1.5-nm direct-tunneling gate SiO₂ CMOS are described. Very high cutoff frequencies of 170 GHz and 235 GHz were obtained for 0.08-μm and 0.06-μm gate length nMOSFETs at room temperature. Cutoff frequency of 65 GHz was obtained for 0.15-μm gate length pMOSFETs using 1.5-nm gate SiO₂ for the first time. The normal oscillations of the 1.5-nm gate SiO₂ CMOS ring oscillators were also confirmed. In addition, this paper investigates the cutoff frequency and propagation delay time in recent small-geometry CMOS and discusses the effect of gate oxide thinning. The importance of reducing the gate oxide thickness in the direct-tunneling regime is discussed for sub-0.1-μm gate length CMOS in terms of high-frequency, high-speed operation     

Hybrid dry-wet chemical etching process for via holes for galliumarsenide MMIC manufacturing

Through the wafer via-hole connections for monolithic microwave integrated circuits (MMIC) manufacturing have been developed by combining reactive ion etching (RIE) and wet chemical spray etching processes for 100-μm-thick gallium arsenide wafers. The dry process is based on the use of SiCl₄-BCl₃-Cl₂ and BCl₃-Cl₂ gas mixtures at room temperature is a reactive ion etcher. The etching parameters are optimized for anisotropic etching, initially, followed by slightly isotropic etching. To remove the residual `lip' and surface roughness, following reactive ion etching, a dynamic wet chemical spray etching based on H₃PO₄-H₂O₂-H₂O at 45°C is used. The combined dry-wet etching approach is used to fabricate <120-μm diameter via-holes in 100-μm-thick GaAs substrates with a wider process latitude. With this process, the authors have achieved >95 percent yield across 3-in wafers. Metallized via-hole contacts to power FET chips show a contact resistance <20 mΩ per via for 5-μ-thick selective gold plating     

An 0.1-μm voidless double-deck-shaped (DDS) gate HJFET withreduced gate-fringing-capacitance

This paper describes a novel double-deck-shaped (DDS) gate technology for 0.1-μm heterojunction FETs (HJFETs) which have about half the external gate fringing capacitance (C_f^ext) of conventional T-shaped gate HJFET's. By introducing a T-shaped SiO₂-opening technique based on two-step dry-etching with W-film masks, we fabricated 0.1-μm gate-openings which were suitable for reducing the C_f^ext and filling gate-metals with voidless. The fine gate-openings are completely filled with refractory WSi/Ti/Pt/Au gate-metal by using WSi-collimated sputtering and electroless Au-plating, resulting in high performance 0.1-μm DDS gate HJFETs are fabricated. The 0.1-μm n-Al _0.2Ga_0.8As/i-In_0.15Ga_0.85As pseudomorphic DDS gate HJFETs exhibited an excellent V_th standard-deviation (σV_th) of 39 mV because dry-etching techniques were used in all etching-processes. Also, an HJFET covered with SiO₂ passivation film had very high performance with an f_T of 120 GHz and an f_max of 165 GHz, due to the low C_f^ext with the DDS gate structure. In addition, a high f_T of 151 GHz and an f_max of 186 GHz were obtained without a SiO₂ passivation film. This fabrication technology shows great promise for high-speed IC applications     

InGaAsP (λ=1.3 μm) strip buried heterostructure lasersgrown by MOCVD

The authors describe InGaAsP-InP index guides strip buried heterostructure lasers (SBH) operating at 1.3 μm with a 1.1-μm guiding layer grown by a two-step atmospheric pressure metalorganic chemical vapor deposition (MOCVD) growth procedure. These lasers are compared with buried heterostructure lasers having similar guiding layers under the active layer but terminated at the edge of the active layer. SBH lasers with 0.15-μm-thick active layer strips, 5-μm wide, and guide layers varying from 0 to 0.7 μm have threshold currents increasing from 34 to 59 mA, and nearly constant differential external quantum efficiencies of 0.2 mW/mA. The threshold current increases more rapidly with temperature with increasing guide layer thickness, with T₀ decreasing from 70°C for lasers without a guide layer to 54.3°C for lasers without a guide layer to 54.3°C for lasers with 0.7-μm-thick guide layers. Output powers of up to 30 mW/facet have been obtained from 254-μm-long lasers and were found to be insensitive to guide layer thickness     

Room temperature pulsed operation of 1.5 μm GaInAsP/InPvertical-cavity surface-emitting laser

Room-temperature pulsed operation of a GaInAsP/InP vertical-cavity surface-emitting laser diode (VCSELD) with an emission wavelength near 1.55 μm is reported. A double heterostructure with a 34-pair GaInAsP (λ_g=1.4 μm)/InP distributed Bragg reflector (DBR) was grown by metalorganic chemical vapor deposition (MOCVD). The measured reflectivity of the semiconductor DBR is over 97% and threshold current is 260 mA for a 40-μmφ device with a 0.88-μm-thick active layer. Threshold current density is as low as 21 kA/cm² at room temperature     

Promising storage capacitor structures with thin Ta2O5 film for low-power high-density DRAMs

To ensure the required capacitance for low-power DRAMs (dynamic RAMs) beyond 4 Mb, three kinds of capacitor structures are proposed: (a) poly-Si/SiO₂/Ta₂O₅/SiO₂ /poly-Si or poly-Si/Si₃N₄/Ta₂O ₅/SiO₂/poly-Si (SIS), (b) W/Ta₂O₅ /SiO₂/poly-Si (MIS), and (c) W/Ta₂O₅ W (MIM). The investigation of time-dependent dielectric breakdown and leakage current characteristics indicates that capacitor dielectrics that have equivalent SiO₂ thicknesses of 5, 4, and 3 nm can be applied to 3.3-V operated 16-Mb DRAMs having stacked capacitor cells (STCs) by using SIS, MIS, and MIM structures, respectively, and that 3 and 1.5 nm can be applied to 1.5-V operated 64-Mb DRAMs having STCs by using MIS and MIM structures, respectively. This can be accomplished while maintaining a low enough leakage current for favorable refresh characteristics. In addition, all these capacitors show good heat endurance at 950°C for 30 min. Therefore, these capacitors allow the fabrication of low-power high-density DRAMs beyond 4 Mb using conventional fabrication processes at temperatures up to 950°C. Use of the SIS structure confirms the compatability of the fabrication process of a storage capacitor using Ta₂O₅ film and the conventional DRAM fabrication processes by successful application to the fabrication process of an experimental memory array with 1.5-μm×3.6-μm stacked-capacitor DRAM cells     

Loss reduction of an ARROW waveguide in shorter wavelength and itsstack configuration

The reduction of the propagation loss of an antiresonant reflecting optical waveguide (ARROW) to 0.3 dB/cm in a short-wavelength band by using transparent TiO₂/SiO₂ interference cladding is discussed. An analysis method for ARROW is developed to analyze its propagation characteristics. Two uncoupled parallel ARROWs were stacked with 2-μm spacing, to obtain three-dimensional optical interconnection     

Low-loss low-confinement GaAs-AlGaAs DQW laser diode with opticaltrap layer for high-power operation

A low-confinement asymmetric GaAs-AlGaAs double-quantum-well molecular-beam-epitaxy grown laser diode structure with optical trap layer is characterized, The value of the internal absorption coefficient is as low as 1.4 cm^-1, while keeping the series resistance at values comparable cm with symmetrical quantum-well gradient index structures in the same material system. Uncoated devices show COD values of 35 mW/μm. If coated, this should scale to about 90 mW/μm. The threshold current density is about 1000 A/cm² for 2-mm-long devices and a considerable part of it is probably due to recombination in the optical trap layer. Fundamental mode operation is limited to 120-180 mW for 6.5-μm-wide ridge waveguide uncoated devices and to 200-300 mW for 13.5-μm-wide ones, because of thermal waveguiding effects. These values are measured under pulsed conditions, 10 μs/l ms     

An InP MISFET with a power density of 1.8 W/mm at 30 GHz

The millimeter-wave power performance of a 75-μm×0.3-μm InP MISFET with SiO₂ insulator is presented. The combination of high intrinsic transconductance (120 mS/mm), current density (1 A/mm), and gate-source and gate-drain breakdown voltages (35 V) led to a record power density of 1.8 W/mm and 20% power-added efficiency at 30 GHz. This power density is the highest ever reported for any three-terminal device at this frequency     

MOS transistors with stacked SiO2-Ta2O5-SiO2 gate dielectrics for giga-scale integration ofCMOS technologies

Advances in lithography and thinner SiO₂ gate oxides have enabled the scaling of MOS technologies to sub-0.25-μm feature size. High dielectric constant materials, such as Ta₂O₅ , have been suggested as a substitute for SiO₂ as the gate material beyond t_ox≈25 Å. However, the Si-Ta ₂O₅ material system suffers from unacceptable levels of bulk fixed charge, high density of interface trap states, and low silicon interface carrier mobility. In this paper we present a solution to these issues through a novel synthesis of a thermally grown SiO₂(10 Å)-Ta₂O₅ (MOCVD-50 Å)-SiO₂ (LPCVD-5 Å) stacked dielectric. Transistors fabricated using this stacked gate dielectric exhibit excellent subthreshold behaviour, saturation characteristics, and drive currents     

Planar AlGaAs/GaAs heterojunction bipolar transistors fabricatedusing selective W-CVD

The authors describe a planar process for the AlGaAs/GaAs HBTs in which collector vias are buried selectively, even to the base layers, with chemical vapor deposited tungsten (CVD-W) films. By using WF₆ /SiH₄ chemistry, W could be deposited on Pt films, which were overlapped 50 nm thick on the AuGe-based collector electrodes, without depositing W on the surrounding SiO₂ layers. Current gains of planar HBTs with 3.5-μm×3.5-μm emitters were up to 150, for a collector current density of about 2.5×10⁴ A/cm²     

GaAs MESFETs on InP substrates grown using chloride close-proximityreactor system

DC and microwave characteristics of GaAs metal-semiconductor field-effect transistors (MESFETs) on InP grown using the chloride close-proximity reactor (CPR) system are reported. The FETs have an extrinsic maximum transconductance of 210 mS/mm for a drain saturation current of 110 mA/mm, a cutoff frequency of unity current gain of 13 GHz, and a maximum frequency of oscillation of 21 GHz. The dislocation density in a 1.6-μm GaAs layer on InP is 10⁸ cm^-2 measured from cross-sectional transmission electron microscopy (TEM). The full width at half maximum of (400) reflection is 270" for a 3-μm-thick GaAs layer     

A micromachined silicon sieve electrode for nerve regenerationapplications

A micromachined silicon sieve electrode has been developed and fabricated to record from and stimulate axons/fibers of the peripheral nervous system by utilizing the nerve regeneration principle. The electrode consists of a 15-μm-thick silicon support rim, a 4-μm-thick diaphragm containing different size holes to allow nerve regeneration, thin-film iridium recording/stimulating sites, and an integrated silicon ribbon cable, all fabricated using boron etch-step and silicon micromachining techniques. The thin diaphragm is patterned using reactive ion etching to obtain different size holes with diameters as small as 1 μm and center-center spacings as small as 10 μm. The holes are surrounded by 100-200 μm² anodized iridium oxide sites, which can be used for both recording and stimulation. These sites have impedances of less than 100 kΩ @ 1 kHz and charge delivery capacities in the 4-6 mC/cm² range. The fabrication process is single-sided, has high yield, requires only five masks, and is compatible with integrated multilead silicon ribbon cables. The electrodes were implanted between the cut ends of peripheral taste fibers of rats (glossopharyngeal nerve), and axons functionally regenerated through holes, responding to chemical, mechanical, and thermal stimuli     

Comparison of high-temperature-superconductor and metal-basedresonators

A 50-Ω coplanar waveguide (CPW) resonator designed for a fundamental frequency of about 4.75 GHz was fabricated on LaAlO₃ . Two versions were fabricated: the first using 1.9-μm-thick gold and the second using 0.6-μm-thick YBa₂Cu₃O ₇. The devices were identically packaged and tested at 77 K. It was found that the high-temperature superconductor (HTS) resonator had a surface resistance, R_s, about six to nine times lower than the Au one. At 45 K, the R_s of the HTS resonator decreases by another factor of 4 compared with its 77 K value. Device characteristics for the HTS resonator are presented     

Planarization of dielectric layers for multilevel metallization

A process to planarize low-pressure chemical-vapor deposition (LPCVD) SiO₂ films formed over the abrupt topography of fine-line (2.0-μm pitch) integrated circuits with two levels of metallization and pillar interconnections has been developed with sacrificial photoresist and plasma etching using response-surface methodology. To produce flat dielectric surfaces with this topography, the ratio of the measured etch rate of photoresist to that of phosphorus-doped SiO₂ must be maintained at ~0.4 (3800 and 9100 Å/min, respectively) with an Ar/CF₄/O₂ high pressure plasma generated in a low radio-frequency etching system     

0.2-μm fully-self-aligned Y-shaped gate HJFET's with reducedgate-fringing capacitance fabricated using collimated sputtering andelectroless Au-plating

This paper reports on new fully-self-aligned gate technology for 0.2-μm, high-aspect-ratio, Y-shaped-gate heterojunction-FET's (HJFET's) with about half the external gate-fringing capacitance (C_f^rext) of conventional Y-shaped gate HJFET's. The 0.2-μm Y-shaped gate openings are realized by anisotropic dry-etching with stepper lithography and SiO₂ sidewall techniques instead of electron beam lithography. By introducing WSi-collimated sputtering and electroless gold-plating techniques for the first time, we have developed a high-aspect-ratio, voidless and refractory Y-shaped gate-electrode without the need for mask alignments. A fabricated 0.2-μm gate n-Al_0.2Ga_0.8As/In_0.2Ga_0.8As HJFET shows very small current saturation voltage of 0.25 V, marked gm _max of 631 mS/mm with 6-V gate-reverse breakdown voltage, and excellent threshold voltage uniformity of 9 mV. Also, the improved rf-performance such as f_T=71 GHz and f_max=120 GHz is realized even with the passivation for the high-aspect-ratio gate-structure with reduced C_f^rext. The developed technology based upon a fully-self-aligned and an all-dry-etching process provides higher performance and uniformity, thus it is very promising for high-speed and low-power-consumption digital and/or analog IC's/LSI's     

Optical waveguides in SIMOX structures

Propagation characteristics determined experimentally and theoretically for planar optical waveguides formed in separation by implantation of oxygen (SIMOX) structures are discussed. All samples were found to support both TE and TM modes at both 1.15 μm and 1.523 μm with a lowest propagation loss of 8 dB/cm. This loss was measured at a wavelength of 1.15 μm for the TE₀ mode of a planar waveguide with a 2.0-μm-thick Si guiding layer     

Flat-field spectrograph in SiO2/Si

The operation of a flat-field spectrograph in silica glass on silicon (SiO₂/Si) as a demultiplexer with 4-nm channel spacing in the 1.5-μm waveguide length region is demonstrated. The concept allows fabrication tolerances to be compensated simultaneously with the adjustment of fan-out. Fiber-to-fiber insertion loss of 10.1 dB and crosstalk attenuation >15 dB have been achieved     

Low threshold room temperature pulsed and -57°C CW operationsof 1.3 μm GaInAsP/InP circular planar buried heterostructuresurface-emitting lasers

Room temperature pulsed lasing operation of a 1.3-μm GaInAsP/InP vertical-cavity surface-emitting laser has been achieved by using an effective carrier confinement of circular planar buried heterostructure (CPBH) and high reflectivity SiO₂/Si dielectric multilayer mirrors. The threshold current for a device having a nearly 12-μm-diameter active region was 34 mA at 24°C under pulsed operation. The optimized window cap structure reduces the series resistance to 6~15 Ω. Continuous wave lasing was also obtained up to -57°C, and the threshold below -61°C was still lower than 22 mA