5GHz高线性度CMOS混频器的设计

文中分析了混频器的线性度与转换增益之间的关系,提出了一种提高Gilbert混频器线性度的方法,并设计了5GHz频段适用于802.11a标准的高线性度混频器.电路采用0.18μm CMOS工艺,通过Cadence SpectreRF仿真与优化,得到10.25dBm的1 dB压缩点,-2.24 dB的转换增益,26 dB的噪声系数,整个混频器达到了较高的线性度.     

一种1V 2.4G CMOS高线性度混频器

本文提出了一种低电压、高线性度CMOS射频混频器.在LC折叠式共源共栅结构中,通过并联一工作在弱反应区的辅助MOS管的方法来改善线性度.在1V的工作电压下,采用TSMC0.18μm射频CMOS工艺仿真表明,该方法在基本不影响混频器其它参数如增益、功耗、噪声的条件下ⅡP3提高了6dB.     

低电压高增益下变频混频器设计

本文设计一个低电压高增益下变频混频器。为了降低电源电压,本文采用了LC-tank折叠结构,同时为了提高混频器线性度,采用了开关对共源节点谐振技术。在低电源电压和高线性得到保证的情况下,本文用ADS2009软件重点对混频器的转换增益进行优化、仿真,结果表明:工作电压1.4V,RF频率2.5GHz,本振频率2.25GHz,中频频率250MHz,转换增益7.325dB,三阶交调点6.203dBm,单边带噪声系数3.823dB,双边带噪声系数2.868dB,功耗14.028mW,本文所设计的混频器可用于无线通信领域的电子系统中。     

基于电感源极退化技术的高线性混频器设计

基于电感源极退化技术设计了一款新颖的高线性度正反馈跨导放大器,并且将该跨导放大器应用于折叠结构式混频器当中。通过抵消反相器和辅助放大器之间的三阶跨导分量,改善了其线性度。电路采用TSMC 0.13μm CMOS工艺进行设计与仿真,完成了版图设计与流片。与传统结构相比,该混频器的输入三阶交调点IIP3高达8.6 dBm,噪声系数为10.9 dB,增益高达14 dB,并且取得了更优的归一化FOM指标。     

基于CMOS模拟开关实现平衡混频器

详细介绍了有源单平衡混频器的电路组成,分析了有源平衡混频器的工作原理。基于CMOS模拟开关设计实现了一种(低功耗、高线性度的)开关平衡混频器,最后对混频器的指标进行了测量和分析。测试结果表明(在3.3V电源电压下,消耗电流小于10mA,射频输入信号)在60～110MHz频带范围内,(本振信号+10dBm时)插入损耗小于7dB,波动小于1dB,输入P1dB压缩点大于13dBm。     

基于噪声抵消和线性度提高的差分LNA的设计

基于TSMC 0.18μm CMOS工艺,设计了一种低噪声、高增益、高线性度的差分CMOS低噪声放大器。与传统的共源共栅结构相比,在共栅极上引入一对交叉耦合电容和电感,以消除共栅极的噪声并提高电路的线性度和增益。仿真结果表明,在2.45GHz的工作频率下,该电路的噪声系数仅有1.3 dB,该电路能够提供17.8 dB的正向增益,良好的输入输出匹配,该放大器的输入三阶交调点为-0.9 dBm,功耗小于10 mW。     

适用于WLAN接收机的高线性电流模式混频器设计

针对无线局域网接收机对低成本和线性度的定制化需求,设计了一款适用于IEEE 802.11 b/g/n/ax标准WLAN接收机的高线性度电流模式混频器;采用零中频接收机架构,电流模式混频器的电路结构主要包括跨导级放大器,混频开关级和跨阻放大器;通过跨导级两种工作状态的转换和跨阻放大器反馈电阻的两种取值变化实现了混频器的四档增益可调;混频开关级选用双平衡无源混频电路以提供良好的线性度;为了解决零中频接收机存在的直流失调问题,加入了一种电流注入式的直流失调校准电路,进一步提高了混频器的线性度;对跨阻放大器中的跨导运算放大器电路进行优化设计以提高其带宽,使跨阻放大器的输入阻抗足够小以保证混频器的线性度;基于180 nm RF CMOS工艺,借助Cadence软件对混频器进行仿真:当本振频率为2.4GHz时,四档增益分别为38dB、32dB、27dB和21dB,中频带宽可达20MHz;噪声系数在高增益的情况下为8.46dB,输入三阶交调点在低增益的情况下可达13.72dBm;仿真结果表明,在较宽的中频带宽下,电流模式混频器取得了良好的线性度性能,满足WLAN接收机的定制化需求。     

一种高线性度的2.4 GHz CMOS功率放大器设计

为了满足目前物联网低成本、低功耗与较高线性度的市场应用需求,提出了一种高线性度的2.4 GHz功率放大器(PA)。该功率放大器为两级结构,为了提高增益的同时保持较低的静态功耗其驱动级采用了电流复用两级共源放大结构,并且使用了两级失真抵消的方法减小了晶体管跨导非线性的影响,同时采用二极管线性化偏置来补偿寄生电容非线性导致的增益压缩现象。该功率放大器采用0.18μm CMOS工艺,后仿真结果表明,在2.4 GHz工作频率下,该PA小信号增益为30 dB,输出1 dB压缩点为22 dBm,静态功耗为53 mW,功率附加效率峰值为31%。     

用于合成孔径辐射计的集成接收机设计

采用0.13μm GaAs pHEMT工艺,提出一种Ka波段低噪声下变频单片式微波集成接收机,可满足合成孔径辐射计应用要求。该设计由4级低噪声放大器模块和由双平衡混频器组成的镜像抑制混频器组成。仿真结果显示,在输入信号频率为29~34GHz时,芯片的变频增益为17~20dB,镜像抑制度超过20dBc,噪声系数为2.6~3dB。     

基于模拟预失真的2.4 GHz CMOS功率放大器设计

基于65 nm互补金属氧化物半导体(CMOS)工艺,设计一种2. 4 GHz的两级全差分功率放大器。通过采用片上变压器实现单端信号和差分信号之间的转换和输入输出阻抗匹配和将驱动级作为预失真器的模拟预失真技术提高线性度,从而实现高增益、高集成度和高线性度的功率放大器芯片。芯片面积为1. 08 mm×1. 37 mm。仿真结果表明:在2. 4 GHz的工作频点,功率放大器的-1 d B输出功率为22. 9 d Bm,功率附加效率为23. 5%,小信号增益为27. 2 d B,三阶交调失真为-35. 6 d Bc。     

Folded down-conversion mixer for a 60 GHz receiver architecture in 65-nm CMOS technology

We present the design of a folded down-conversion mixer which is incorporated at the final down-conversion stage of a 60 GHz receiver. The mixer employs an ac-coupled current reuse transconductance stage. It performs well under low supply voltages, and is less sensitive to temperature variations and process spread. The mixer operates at an input radio frequency （RF） band ranging from 10.25 to 13.75 GHz, with a fixed local oscillator （LO） frequency of 12 GHz, which down-converts the RF band to an intermediate frequency （IF） band ranging from dc to 1.75 GHz. The mixer is designed in a 65 nm low power （LP） CMOS process with an active chip area of only 0.0179 mm^2. At a nominal supply voltage of 1.2 V and an IF of 10 MHz, a maximum voltage conversion gain （VCG） of 9.8 dB, a double sideband noise figure （DSB-NF） of 11.6 dB, and a linearity in terms of input 1 dB compression point （Pin, 1dB） of-13 dBm are measured. The mixer draws a current of 5 mA from a 1.2 V supply dissipating a power of only 6 roW.     

Third-order intermodulation in a micromechanical thermal mixer

A radio frequency (RF) micromechanical shell-type resonator with a resistive thermal actuator is shown to perform as a highly linear, broadband mixer and a high-quality factor post-translation (intermediate frequency) filter. The resistor is capable of frequency translation of RF carrier signals as high as 1.5 GHz to the intermediate frequency of 12.7 MHz. The thermal actuator allows electrical isolation between the input and output of the mixer-filter, dc bias independent mixing, and provides a 50-Ohm load to match the output of front-end electronics. High linearity is demonstrated in the mixer with a third-order input intercept point of +30 dBm for interferers spaced at a 50-kHz offset from the carrier frequency. A variant of the Duffing oscillator model and finite element modeling are used to analyze the origin of nonlinearities in the micromechanical system. [1503].     

一种应用于2．4GHz的使用新匹配的混频器

提出了一种带有输入匹配网络优化的上变频MIXER电路。通过使用全新的输入匹配网络,不仅满足MIXER电路的匹配要求,同时更使电路较少使用了电感元件,使电路版图大大减小。提出的MIXER采用0．18μmSiGeBiCMOS工艺,工作频率为2．4GHz。结果表明,提出的窄带HBTMIXER电路,在2．4GHz频段测试增益,噪声,功耗都符合要求,达到了较好的匹配效果,有较好的稳定性,满足了接收机对MIXER的指标要求。     

Analysis and design of packaged and ESD protected BiCMOS RF front‐end for a UHF receiver

The design of packaged and ESD protected RF front‐end circuits for UHF receiver working at ISM band is presented. By extensively evaluating the effects of the package and ESD parasitics on the LNA input impedance, transconductance, and noise figure, some useful guidelines on the design of inductively degenerated common emitter LNA with package and ESD protection are provided. In addition, by taking advantage of both the bipolar and MOSFET devices, a BiFET mixer with low noise and high linearity is also described in this article. With the careful consideration of the tradeoffs among noise figure, linearity, power gain, and power consumption, the front‐end is implemented in a generic low‐cost 0.8‐μm BiCMOS technology. The on‐board measurement of the packaged RF front‐end circuits demonstrates a 20.3‐dB power gain, 2.6‐dB DSB noise figure, and ?9.5‐dBm input referred third intercept point while consuming about 3.9‐mA current. © 2007 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2007.     

Self‐oscillating mixer using six port power divider

A self‐oscillating mixer (SOM) that uses a six port microstrip power divider is presented in this article. The oscillation and mixing functions are executed using a pair of identical GaAs field effect transistors. The power division and combination of the RF and local oscillator (LO) signals involved in the operation are implemented using the six port network. The RF input port of the proposed SOM is totally isolated from the operation of the LO which is a desirable feature in many applications. The proposed structure can work as a stand‐alone oscillator with a frequency of 4.71 GHz and a power level of 16.1 dBm. When fed with a RF signal, the proposed structure becomes a fully functional SOM exhibiting a conversion gain of 5.2 dBm. The simulation and measurement results of the proposed SOM are presented to validate the design concept. © 2014 Wiley Periodicals, Inc. Int J RF and Microwave CAE 25:269–276, 2015.     

Design of MEMS switch for RF applications

Components like passive electronically scanned (sub) arrays, T/R modules, reconfigurable antennas etc., in RF applications are in need of MEMS switches for its re-configurability and polarization. This paper presents the analysis, design and simulation of a MEMS switch. The switch proposed in this paper is intended to work in the frequency range of 4–8 GHz. The proposed switch fulfills the switching characteristics concerning the five requirements loss, linearity, high switching speed, small size/power consumption, low pull down voltage following a relatively simple design, which ensures reliability, robustness and high fabrication yield. The switch implemented in this paper is based on the integration mode of operation and widely used in RF applications.     

A low conversion loss single balanced subharmonic mixer

A new circuit topology for the design of a single balanced second‐order subharmonic mixer (SHM) is proposed. In the proposed topology, it is not necessary for the radio frequency (RF) and local oscillator (LO) signal to be within 15% frequency difference. Thus, the limitation of a conventional rat‐race mixer has been alleviated. Moreover, it shows very low conversion loss, high LO‐to‐RF, LO to intermediate frequency (IF), and 2LO‐to‐RF port isolations. The measured minimum down conversion loss is 5.8 dB at 13 GHz and remains below 7.65 dB over the 2 GHz RF operational band 12‐14 GHz for a fixed IF of 550 MHz. Measured LO‐to‐RF and LO‐to‐IF port isolations are better than ?40 dB over the entire operational band. The 2LO‐to‐RF isolation is more than ?62 dB which is extremely necessary for a second harmonic mixer where 2LO and RF frequency are close to each other. The input 1‐dB compression point is measured to be ?1 dBm.     

3GHz～5GHz CMOS超宽带低噪声放大器设计

提出了一个低噪声、高线性的超宽带低噪声放大器(UWB LNA).电路由窄带PCSNIM LNA拓扑结构和并联低Q负载结构组成,采用TSMC 0.18 μm RFCMOS工艺,并在其输入输出端引入了高阶带通滤波器.仿真结果表明,在1.8V直流电压下LNA的功耗约为10.6 mW.在3 GHz～5 GHz 的超宽带频段内,...