Reduction of floating substrate effect in thin-film SOI MOSFETs

The presence of a floating substrate in SOI transistors gives rise to a decrease of threshold voltage when drain voltage is increased. When the devices are made in a very thin silicon film, the latter is completely depleted when the device is in the 'on' state, and no part of the film can act as a floating substrate. This brings about a dramatic decrease of the so-called 'kink effect'.     

Special mechanisms in thin-film SOI MOSFETs

The main special mechanisms that govern the operation of thin-film SOI MOSFETs are reviewed. The influence of the most important technological and electrical parameters, e.g. the film and buried oxide thicknesses, film and silicon substrate doping, channel length, substrate bias, and interface defects, is discussed. The electrical properties of fully depleted thin-film SOI MOS transistors are improved, especially the driving current and the subthreshold swing. We address the advantages of thin-film SOI devices in relation to scaling rules down to deep submicron transistors, as well as the main parasitic phenomena, e.g. the kink, latch, breakdown, self-heating and hot-carrier degradation effects. Finally, the low temperature properties and potential quantum effects are outlined.     

Subthreshold slope in thin-film SOI MOSFETs

The subthreshold conduction regime in thick- and thin-film SOI MOSFETs is studied. Using the depletion approximation, a one-dimensional analytical expression for the subthreshold slope is derived, and equivalence with a simple capacitive network is proven. The model accounts for the influence of the back interface properties on the subthreshold swing in the thin-film regime. The coupling between front and back surface potential and the influence of the backside conduction on the front interface characteristics are accounted for. The case of double gate control is studied in more detail. Experimental verification of the model with measured subthreshold slopes in thin-form MOSFET devices is given     

Enhanced substrate current in SOI MOSFETs

This letter reports an enhanced substrate current at high gate bias in SOI MOSFETs. A comparison between coprocessed bulk and partially depleted SOI MOSFETs is used to present the enhancement unique to SOI devices and demonstrate the underlying mechanism. Other than electric field, a new source for carrier heating in the channel, i.e., self-lattice heating, is found to be responsible for the excess substrate current observed. The impact of this phenomenon on SOI device lifetime prediction and compact modeling under dynamic operating conditions typical of digital circuit operation is described. This SOI-specific enhancement must be considered in one-to-one comparisons between bulk and SOI MOSFETs regarding hot-carrier effects     

Reduction of kink effect in thin-film SOI MOSFETs

Numerical simulation is used to show that potential and electric field distribution within thin, fully depleted SOI devices is quite different from that observed within thicker, partially depleted devices. Reduction of drain electric field and of source potential barrier brings about a dramatic decrease of kink effect     

Numerical and charge sheet models for thin-film SOI MOSFETs

Numerical charge sheet models applicable for all bias conditions are presented for the channel currents of long-channel SOI MOSFETs. From a comparison of the two models it is shown that the charge sheet analytic model accurately predicts the channel currents from weak to strong inversion regions. The results include analytic expressions for the drift and diffusion current components of individual channel currents, the front-gate and back-gate interaction parameter, and an analytic correlation between the surface potentials of the front and back channels when there is coupling between the two gates under nonthermal equilibrium conditions. The effect of SOI (silicon on insulator) film thickness on the drain current was investigated under different bias conditions for the back gate, and it was found that thin films are beneficial from the point of increased drain currents if the back channel is in depletion or inversion. It is also shown that, in addition to the charge coupling effects, dynamic interaction between the channels exists if the static current in one of the channels saturates     

On the high-temperature subthreshold slope of thin-film SOI MOSFETs

This paper addresses the validity of the classical expression for the subthreshold swing (S) in SOI metal-oxide semiconductor field effect transistors (MOSFETs) at high temperature. Using numerical simulation, it is shown that two effects invalidate the classical expression of S at high temperature. Firstly, the depletion approximation becomes invalid and intrinsic free carriers must be taken into account to determine the effective body capacitance. Secondly, the charge-sheet model for the inversion layer becomes inaccurate due to a lowering of the electric field at the surface and a broadening of the inversion layer thickness in weak inversion. These effects must be taken into account to predict accurately the high-temperature subthreshold characteristics of both partially depleted and fully depleted SOI MOSFETs     

Back-channel hot-electron effect on the front-channelcharacteristics in thin-film SOI MOSFETs

The front-channel I-V characteristics in thin-film SOI MOSFETs have been studied before and after back-channel hot-electron stress. As a result of electron trapping in the buried oxide near the drain junction, this stress causes the following changes: (1) a reduction of the channel current for a given gate voltage; (2) the appearance of the kink effect when measured in the reverse mode (with source and drain interchanged); and (3) an increased breakdown voltage when measured in the reverse mode. Both the kink effect and the change in the breakdown behavior can be attributed to the increased barrier height of the drain-body junction resulting from the localized electron trapping in the buried oxide     

Measurement of substrate current in SOI MOSFETs

A new “Quasi-SOI” MOSFET structure is shown to allow direct measurement of substrate current in a fully-depleted SOI device. The holes generated by impact ionization near the drain are collected at the substrate terminal after they have traversed the source-body barrier and caused bipolar multiplication. By monitoring this hole current, direct characterization of the impact-ionization multiplication factor, M, and the parasitic bipolar gain, β, was performed. It was found that M-1 increases exponentially with V_DS and decreases with V_GS, exhibiting a drain field dependence. The bipolar gain β was found to be as high as 1000 for V_GS-V_T=0 V and V_DS=-2.5 V, but decreases exponentially as V_DS increases. Finally, it was found that β also decreases as V_GS increases     

Analytical expressions for subthreshold charges and currents in thin-film SOI MOSFETs

Analytical expressions for the front and back channel charges and currents in thin-film SOI MOSFETs operating in the subthreshold region are presented, based on a charge sheet model. The analysis includes the charge coupling between the front and back gates and the effect of interface states.<>     

Threshold voltage instability at low temperatures in partiallydepleted thin-film SOI MOSFETs

A threshold voltage instability phenomenon at low temperatures in partially depleted thin-film silicon-on-insulator (SOI) SIMOX (separation by implantation of oxygen) MOSFETs is reported. This phenomenon was investigated under normal MOSFET operating conditions for temperatures ranging from 300 K down to 10 K, with both the magnitude and duration of the instability observed to be strongly dependent on temperature. Threshold voltage shifts as small as 0 V at room temperature and as large as 0.29 V at 10 K are reported. The duration of the instability ranged in the tens of minutes and was observed to increase as the temperature was decreased     

Threshold voltage model for deep-submicron fully depleted SOI MOSFETs with back gate substrate induced surface potential effects

A simple analytical threshold voltage model for short-channel fully depleted SOI MOSFETs has been derived. The model is based on the analytical solution of the two-dimensional potential distribution in the silicon film (front silicon), which is taken as the sum of the long-channel solution to the Poisson's equation and the short-channel solution to the Laplace equation, and the solution of the Poisson's equation in the silicon substrate (back silicon). The proposed model accounts for the effects of the back gate substrate induced surface potential at the buried oxide-substrate interface which contributed an additional 15–30% reduction in the threshold voltage for the devices used in this work. Conditions on the back gate supply voltage range are determined upon which the surface potential at the buried oxide-substrate interface is accumulated, depleted, or inverted. The short-channel associated drain induced barrier lowering effects are also included in the model. The model predications are in close agreement with PISCES simulation results. The equivalence between the present model and previously reported models is proven. The proposed model is suitable for use in circuit simulation tools such as Spice.     

Surface potential at threshold in thin-film SOI MOSFET's

The usual condition for threshold in bulk MOSFETs, of equal rates of change with gate voltage of the inversion and bulk charges, is suitably modified to describe threshold in fully depleted SOI MOSFETs. Using this modified condition the value of the surface potential at threshold in fully depleted transistors is obtained analytically in terms of device dimensions, film doping level, and applied voltages. The results are in excellent agreement with one-dimensional numerical simulations, and it is shown that the surface potential at threshold may differ significantly from 2φ_F, the value conventionally assumed     

On the body-source built-in potential lowering of SOI MOSFETs

This letter provides a viewpoint for the characterization of state-of-the-art thin film silicon-on-insulator (SOI) MOSFETs. Based on body-source built-in potential lowering, the degree of full depletion can be quantified. In addition to serving as a measure of the floating-body behavior of SOI devices, the concept also enables the consolidation of partial-depletion (PD) and full-depletion (FD) SOI compact models. This consolidation of compact models together with the trend of coexistence of PD/FD devices in a single chip has become one of the greatest challenges in the scaling of SOI CMOS.     

基于粒子群优化算法的BSIM SOI模型参数提取

本文给出一种基于粒子群优化算法的BSIM SOI MOSFETs模型参数提取方法.该方法采用全局优化策略,计算简单,对初值依赖性低,使用浮点数编码方法,避免了数码转换时所出现的误差.与遗传算法参数提取相比,粒子群优化算法无需进行交叉、变异等操作,容易理解,易于实现,且收敛速度更快.对用该方法得到的参数值代入器件模型进行了计算,计算结果与测试结果吻合很好.本方法亦可用作对其他种类的MOSFETs进行全局参数提取.     

纳米尺度全耗尽SOI MOSFET阈值电压的修正模型

针对纳米器件中出现的量子化效应,考虑了薄层全耗尽SOI MOSFET沟道反型层电子的量子化,研究了反型层量子化效应对阈值电压的影响。结果表明,沟道反型层的量子化效应导致阈值电压增大,推导并给出了纳米尺度全耗尽SOI MOSFET的阈值电压修正模型。     

全耗尽SOI MOSFETs阈值电压解析模型

提出了一种新的全耗尽SOI MOSFETs阈值电压二维解析模型.通过求解二维泊松方程得到器件有源层的二维电势分布函数,氧化层-硅界面处的电势最小值用于监测SOI MOSFETs的阈值电压.通过对不同栅长、栅氧厚度、硅膜厚度和沟道掺杂浓度的SOI MOSFETs的MEDICI模拟结果的比较,验证了该模型,并取得了很好的一致性.     

Analytical one-dimensional current-voltage model for FD SOI MOSFETs including the effect of substrate depletion

In this paper, we present an analytical one-dimensional current-voltage model for silicon-on-insulator (SOI) MOSFETs under full depletion (FD). Our model has been developed from the first principles, and it not only includes the effects of source-drain series resistances, self-heating, and parasitic BJT, which are essential to FD SOI device modeling, but also includes another important effect of substrate depletion, for the first time in the literature, which is of vital significance for FD SOI devices having small film thickness and low substrate doping. The results of the drain current obtained from our model show a much better match with the experimental data, with the maximum error being only 9.41%, which is reasonably lower than the maximum error of 15.04% produced by the model of Yu et al., and marginally better than the error of 11.5% of the model of Hu and Jang. It must be noted that, though the improvements achieved in terms of accuracy are not that significant, yet unlike other models, ours is based on a simplified one-dimensional analytical approach, which is absolutely free from iterations, and hence, there is a huge improvement in terms of computational efficiency, which establishes its practical significance.     

An Analytical Threshold Voltage Model for Fully Depleted SOI MOSFETs

提出了一种新的全耗尽SOI MOSFETs阈值电压二维解析模型.通过求解二维泊松方程得到器件有源层的二维电势分布函数,氧化层-硅界面处的电势最小值用于监测SOI MOSFETs的阈值电压.通过对不同栅长、栅氧厚度、硅膜厚度和沟道掺杂浓度的SOI MOSFETs的MEDICI模拟结果的比较,验证了该模型,并取得了很好的一致性.