输入缓冲结构ATM交换网络的窗口接入机理研究

本文了输入缓冲结构ＡＴＭ交换网络的窗口接入机理，首先分析了一种传统的相关窗口接入（ＤＷＡ）机理的最大吞吐率性能，然后，提出了一种独立的窗口接入（ＩＷＡ）机理，ＩＷＡ能彻底消除采用传统的ＤＷＡ机理时在输入缓冲器窗口中存在的队头阻塞现象，借助于概率母函数的方法分析了采用该ＩＷＡ机理的输入缓冲ＡＴＭ交换网络的时延和吞吐率性能，给出了求解平均信元时延和最大吞吐率的封闭显式，分析表明，ＩＷＡ机理的性能比传统     

Improved Multicast Traffic Scheduling Scheme in the Packet-Switching Systems

1　Introduction　THEInternettrafficisexplodingasitisdoublingeveryyear[1 ] .Withtheinventionandevolutionoffiber optictechnologies ,suchastheDWDM[2 ] inthebackbonenetworks,thecarryingcapacityoffiberlinksisdoublingevery 1 2monthsandprovideshigh speednetworkfabrictomeetthefutureband widthdemands.However,accordingtotheMoore sLaw ,thecomputingpowerwillonlydoubleevery1 8months,hencetherouterswillinevitablybecomebottleneckintheInternet.　ManyemergingInternetapplicationsareone to manyormany to man…     

一种新的太比特级交换网络及其工程实现

太比特路由器的研制涉及许多关键技术，其中具有庞大交换容量的可扩展交换网络是最重要的核心技术之一。虽然目前出现了多种路由器交换网络技术，但是由于现有器件和工艺水平的限制，它们的交换容量都难以达到太比特级。因此如何采用创新的体系结构以突破现有技术水平的限制成为设计太比特级交换网络的关键。本文介绍了一种新的具有创新体系结构的太比特级交换网络，并提出了这种交换网络的工程实现方案。     

Performance enhancement of multistage interconnection networks withunit step buffering

Multistage interconnection networks (MINs) have been widely used for parallel computer systems, and also recognized as an efficient switching fabric for digital communication. In this paper, we propose a new switching mechanism for MINs called unit step buffering (USB) which significantly improves the network performance. Here each cell is allowed to move only one buffer entry position using short network cycle. The proposed USB scheme is compared to the traditional scheme by analytical modeling and computer simulation. They reveal that throughput and delay are improved about 60%-80% for practical size MINs with reasonable traffic in the asynchronous transfer mode (ATM) switching environment. Improvement on parallel computer systems with larger size packets is more significant at about 100%. More importantly, the scheme does not require any additional hardware or operational overhead     

一种多级多平面分组交换结构中的带宽保证型调度算法

多级多平面分组交换结构MPMS以其优异的可扩展性正成为新一代交换路由设备的交换核心。但MPMS结构中的调度算法却往往比较复杂。该文提出了一种MPMS结构的带宽保证型调度算法BG-CRRD,该算法将分组流预留带宽信息引入判决机制,仿真实验表明,BG-CRRD在Bernoulli均匀流量条件下可以获得100%的吞吐率,在非均匀流量条件极坏情况下获得高达92%的吞吐率,在过载情况下根据预定带宽分配输出链路带宽。     

直接互连结构中支持优先级业务的自适应路由算法

直接互连结构(Direct Interconnection Network,DIN)具有较好的分布式特性逐渐作为可扩展数据交换结构的核心。在数据交换应用中支持服务质量(Quality of Service,QoS)是一个重要的指标。为此,该文捉出了在DIN结构中支持公平带宽分配和支持优先级业务的路由算法。考虑到在这类结构中路由机制和交换单元的调度策略之间存在紧密联系,该文结合路由机制和调度策略,提出了一种直接互连结构巾支持优先级业务的自适应路由(PrioritySupporting Adaptive Routing,PSAR)算法。该路由算法可公平分配输出带宽给各个输入端口,同时支持优先级业务。仿真实验验证了公平分配输出带宽和对优先级业务的支持。     

MSM型Clos交换结构及算法的OPNET建模与仿真

交换结构是交换机的核心,决定着交换机的性能。MSM型Clos交换结构是一种高性能交换结构,为有效仿真分析该交换结构建立了一种OPNET仿真模型。该模型将交换系统抽象为一个星型网络,其边缘节点对应交换结构输入和输出,中心节点对应MSM型Clos交换结构;并使用此模型仿真分析了3种典型算法的性能。该模型为交换结构性能的仿真分析提供了一种有效途径。     

一种新的基于CNN调度信元的输入缓冲ATM交换结构

提出了基于细胞神经网络 (CNN)调度信元的输入缓冲ASF方案 ,该方案消除了队头阻塞造成的输入缓冲ASF性能恶化。计算机仿真表明 ,该方案非常有效 ,其性能接近于输出缓冲ASF。     

多平面ATM交换网络结构及其性能分析

本文提出一种新的多平面ＡＴＭ交换网络结构。该结构比单平面结构有更好的性能,并且在网络平扩容和冗余备份等方面均具有优良的特性。通过采用虚拟队列和概率母函数的方法,分析了在随机均匀业务模型下该交换网络缓存器的平均队长、平均信元时延和交换网络最大吞吐率等性能参数的封闭表达式,计算机仿真结果表明了分析结果具有很高的精确度。该分析方法不需复杂的叠代算法,在交换机的工程设计中同时也具有重要的实际意义。     

多维分组交换结构中的一种缓存设置方法

分析了在多维分组交换结构（MPSF, multi-dimensional packet switching fabric）中,采用传统的缓存设置方法时存在的缺陷.为此,提出了一种新的缓存设置方法.该方法可简化交换节点调度策略的实现,提升交换结构的吞吐量.分析和仿真结果验证,相比与传统的在MPP （massively parallel processor）中采用的缓存设置方法,采用新方法可获得更好的吞吐量性能,且降低实际开销.     

CLOS网络型大规模ATM交换结构

首先提出了大规模ＡＴＭ交换网络应满足的基本特性，然后对Ｃｌｏｓ网络型大规模ＡＴＭ交换网络进行了研究，给出了交换网络连接级呼叫的无阻塞条件，论述和分析了一种适合于以信元为单位的分散式路由选择算法。     

An optical packet switch based on WDM technologies

Dense wavelength-division multiplexing (DWDM) technology offers tremendous transmission capacity in optical fiber communications. However, switching and routing capacity lags behind the transmission capacity, since most of today's packet switches and routers are implemented using slower electronic components. Optical packet switches are one of the potential candidates to improve switching capacity to be comparable with optical transmission capacity. In this paper, we present an optically transparent asynchronous transfer mode (OPATM) switch that consists of a photonic front-end processor and a WDM switching fabric. A WDM loop memory is deployed as a multiported shared memory in the switching fabric. The photonic front-end processor performs the cell delineation, VPI/VCI overwriting, and cell synchronization functions in the optical domain under the control of electronic signals. The WDM switching fabric stores and forwards cells from each input port to one or more specific output ports determined by the electronic route controller. We have demonstrated with experiments the functions and capabilities of the front-end processor and the switching fabric at the header-processing rate of 2.5 Gb/s. Other than ATM, the switching architecture can be easily modified to apply to other types of fixed-length payload formats with different bit rates. Using this kind of photonic switch to route information, an optical network has the advantages of bit rate, wavelength, and signal-format transparencies. Within the transparency distance, the network is capable of handling a widely heterogeneous mix of traffic, including even analog signals.     

太比特路由器多元超立方体交换结构时延性能分析

在交换结构的设计中引入多元超立方体静态互连技术，本文提出了一种新的分布式多机架太比特级交换网络：多元超立方体交换结构(MHSF)和相关的汉明随机路由算法(MRRA)。理论分析表明，当各交换节点的流量均匀地发送到各个目的节点时，信元通过MHSF的平均时延有确定的上界。在一定的链路加速因子条件下，MHSF具有可接受的平均时延。     

Hierarchical path hunt in a broadband multirate circuit switchingfabric

A circuit switching fabric that switches narrowband (DS0), wideband (N×DS0, N×VT), and broadband (STS-N) signals embedded in SONET streams is studied. Based on the Clos (1953) strictly nonblocking principle, the fabric is strictly nonblocking if all path hunts are performed at the basic-rate (DS0 in our case) level. On the other hand, a hierarchical path hunt can speed up the path hunt process for a high bit-rate call, though the fabric will then lose its nonblocking property. We study several hierarchical path hunt algorithms and investigate how the hierarchy impacts the blocking probability. We also study the performance impact resulting from doing broadcast/multicast in a multirate circuit switching fabric. Our results provide insights into how hierarchical path hunts should be designed in a broadband multirate circuit switching fabric     

A central-stage buffered three-stage Clos switching fabric and the scheduling algorithm

Current MSM switching fabric has poor performance under unbalanced traffic. This paper presents an alternative, novel Central-stage Buffered Three-stage Clos switching (CB-3Clos) fabric and proves that this fabric can emulate output queuing switch without any speedup. By analyzing the condition to satisfy the central-stage load-balance, this paper also proposes a Central-stage Load-balanced-based Distributed Scheduling algorithm (CLDS) for CB-3Clos. The results show that, compared with Concurrent Round-Robin based Dispatching (CRRD) algorithm based on MSM, CLDS algorithm has high throughput irrespective with the traffic model and better performance in mean packet delay.     

Design issues in ultra-fast ultra-low-power superconductor Batcher-banyan switching fabric based on RSFQ logic/memory family

The results are presented of the feasibility study of ultra-fast low-power superconductor digital switches based on Rapid Single-Flux-Quantum (RSFQ) technology. RSFQ-based crossbar, Batcher-banyan, and shared bus switching fabrics are considered, and the complexity and performance parameters of these circuits have been estimated. The results show that the proposed SFQ digital switches with overall throughput of 5.76 Tbps operating at an internal clock frequency of ∼60 GHz and dissipating as low as 45 mW power per fabric could effectively compete with their semiconductor and photonic counterparts. The most compact and low-power architecture, the Batcher-banyan switching fabric with TDM switching elements, has been selected for implementation and will be discussed in the paper in detail.     

Benes switching fabrics with O(N)-complexity internal backpressure

Multistage buffered switching fabrics are the most efficient method for scaling packet switches to very large numbers of ports. The Benes network is the lowest-cost switching fabric known to yield operation free of internal blocking. Backpressure inside a switching fabric can limit the use of expensive off-chip buffer memory to just virtual-output queues in front of the input stage. This article extends the known credit-based flow control (backpressure) architectures to the Benes network. To achieve this, we had to successfully combine per-flow backpressure, multipath routing (inverse multiplexing), and cell resequencing. We present a flow merging scheme that is needed to bring the cost of backpressure down to O(N) per switching element, and for which we have proved freedom from deadlock for a wide class of multipath cell distribution algorithms. Using a cell-time-accurate simulator, we verify operation free of internal blocking, evaluate various cell distribution and resequencing methods, compare performance to that of ideal output queuing, the iSLIP crossbar scheduling algorithm, and adaptive and randomized routing, and show that the delay of well-behaved flows remains unaffected by the presence of congested traffic to oversubscribed output ports.     

A high-performance switch fabric for integrated circuit and packet switching

This paper describes an architecture for a high-performance switching fabric that can accommodate circuit-switched and packet-switched traffic in a unified manner. The switch fabric is self-routeing and uses fixed-length minipackets within the switching fabric for all types of connections. Its kernel architecture is based on a routeing topology with individual connection paths from all inputs to all outputs and with FIFO queuing at each output. Owing to the disjoint connection paths, there is no internal blocking, and because of output queueing, output port blocking is prevented to a great extent. The uniformity in architecture allows construction of any size fabric from a single basic module which could be realized on a single chip. Larger-size configurations can be realized either as single-stage or multistage configuration. The second part of this paper discusses performance aspects and gives results and dimensioning guidelines for both circuit-switched and packet-switched traffic.     

A Predictor Switching Scheme for DPCM Coding of Video Signals

In DPCM coding of video signals, for improved data compression efficiency, the predictor is often switched adaptively between two or more different predictions. For low-bit-rate coders, the predictor switching is done on a pel-by-pel basis. In this paper, a new scheme for predictor switching on a pel-by-pel basis is proposed. This new scheme is a modification of an existing adaptive predictor switching scheme which has been implemented in pel-recursive motion compensated coding of video signals. To evaluate the efficiency of the new scheme, a theoretical expression for the output bit rate is derived. It is pointed out under what conditions it is advantageous to use the new scheme for predictor switching. Some details of implementation are discussed. Results of computer simulation on natural scenes are presented. These results validate the theoretical conclusions derived in the paper. The simulation results also indicate that the picture quality is improved significantly, for approximately the same output bit rate, with the new predictor switching scheme as compared to the existing scheme for predictor switching.     

An 8?×?8 20?Gbps Reconfigurable Load Balanced TDM Switch IC for High-Speed Networking

In this paper, we propose a reconfigurable load balanced symmetric TDM switch fabric. We fold this two-stage switch to reduce 50% hardware complexity, and then implement a 3.65?mm?×?3.57?mm prototype switch fabric IC, including a digital 8?×?8 switch core, eight 16B20B CODECs, eight SERDES ports, eight CML I/O interfaces and a PLL, in 0.18???m CMOS technology. The digital 8?×?8 switch core has reconfigurable connection patterns for the ease of scaling up to an N×N switch (N is power of 4). We propose the 16B20B CODEC scheme to reduce the switch core clock rate by half. In the SERDES, we employ the half-rate scheme and then use static CMOS gates for the low power consumption. We develop a low power, area-efficient and wide-band CML I/O interface with our patented PMOS active load inductive-peaking scheme for high-speed data transmission. With the 16B20B CODEC, the half-rate, and the PMOS active load schemes, almost 50% of the power is saved as compared with the design of the 8B10B CODEC, the full-rate and on-chip inductors CML schemes. Our measurement shows that an 8?×?8 switch fabric IC can achieve 20?Gbps switching rate and consumes only about 690?mW power. A terabit switch fabric can then be constructed by cascading the designed switch ICs.