A 4-GS/s 4-bit Flash ADC in 0.18- μm CMOS

A 4-bit noninterleaved flash ADC implemented in 0.18-mum digital CMOS achieves a sampling rate of 4 GS/s. A 32 mum by 32 mum, on-chip differential inductor in each comparator extends the sampling rate without an increase in power consumption. A combination of DAC trimming and comparator redundancy reduces the measured DNL and INL to less than 0.15 LSB and 0.24 LSB, respectively. The measured ENOB with a 100 MHz full-power input is 3.84 bits and 3.48 bits, at 3 GS/s and 4GS/s, respectively. The ADC achieves a bit error rate of less than 10^-11 at 4 GS/s.     

A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier for an IR-UWB receiver

A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier(THA) in 0.13μm CMOS for an impulse radio ultra-wideband(IR-UWB) receiver is presented.The challenge is in implementing a sub-sampling ADC with ultra-high input signal that further exceeds the Nyquist frequency.This paper presents,to our knowledge for the second time,a sub-sampling ADC with input signals above 4 GHz operating at a sampling rate of 1.056 GHz.In this design,a novel THA is proposed to solve the degradation in amplitude and improve the linearity of signal with frequency increasing to giga Hz.A resistive averaging technique is carefully analyzed to relieve noise aliasing.A low-offset latch using a zero-static power dynamic offset cancellation technique is further optimized to realize the requirements of speed,power consumption and noise aliasing.The measurement results reveal that the spurious free dynamic range of the ADC is 30.1 dB even if the input signal is 4.2 GHz sampled at 1.056 GS/s.The core power of the ADC is 30 mW,excluding all of the buffers,and the active area is 0.6 mm~2.The ADC achieves a figure of merit of 3.75 pJ/conversion-step.     

A 1-V 1.25-GS/S 8-Bit Self-Calibrated Flash ADC in 90-nm Digital CMOS

We present an 8-bit 1.25-GS/s flash analog-to-digital converter (ADC) in 90-nm digital CMOS with wide analog input bandwidth and low power dissipation. The ADC employs two key techniques: a self-biased track-and-hold amplifier which enhances the ADC full-scale voltage and enables the converter operating under a single 1-V supply; and an improved calibration scheme based on reference pre-distortion to enhance the ADC linearity without sacrificing its sampling speed. The prototype converter thus achieves 7-, 6.9-, 6.5–bit ENOB at 1.25 GS/s for input signal frequencies of 10 MHz, 600 MHz, and 1.3 GHz, respectively, and better than 52-dB SFDR across the full Nyquist-band, while dissipating 207 mW from a single 1-V supply.      

Ku-band subsampling track-and-hold amplifier with 8 ENOB resolution

A wideband subsampling track-and-hold amplifier has been designed for input frequencies up to Ku-band and clock rates up to 2.5 GS/s. Circuits were fabricated in 1 /spl mu/m InP SHBT technology. Spur-free dynamic range measured with two-tone input frequencies of 12.6 and 12.602 GHz and a 2.5 GS/s clock rate ranges from 53-69 dB at an input level of -1 dBFS for each tone. Signal-to-noise ratio (SNR) test results show that the master/slave (M/S) track-and-hold design provides 59 dB of SNR in a 1 GHz bandwidth at input frequencies up to at least 2.6 GHz. A single track-and-hold dissipates 1.5 W while the M/S configuration dissipates 2.5 W.     

A 1 GHz Digital Channel Multiplexer for Satellite Outdoor Unit

A digital channel multiplexer for satellite outdoor unit running at 1 GHz clock frequency is implemented in 65 nm CMOS mixed oxide dual voltage technology. This multiplexer, based on a 1 GS/s digital signal processor (DSP) approach with 500 MHz input and output bandwidth, embeds two 8 bit 1 GS/s analog-digital converters (ADCs) and two 8 bit 1 GS/s digital-analog converter (DACs). It consumes less that 1022 mW at ambient temperature while achieving noise rejection up to 42.5 dB on a single tone, and > 37 dB on modulated satellite channels.     

用于14位1.25 GS/s ADC的跨导运算放大器

设计了一种用于14位1.25 GS/s 流水线ADC的全差分的跨导运算放大器(OTA)。采用带正反馈和增益自举电路的套筒式两级混合密勒补偿结构,并在传统密勒补偿结构基础上增加了带一组调零电阻的辅助密勒补偿结构。这两种补偿结构使得频率补偿更加灵活。对OTA的零极点进行理论分析和整体传递函数解析,再进行传递函数重构,进而实现了高增益、大带宽和高相位裕度。仿真结果表明,该OTA的增益带宽积大于17 GHz,开环增益大于94 dB。该OTA完全满足14位1.25 GS/s流水线ADC的性能要求。     

A 5-b 10-GSample/s a/D converter for 10-gb/s optical receivers

A 5-b flash A/D converter (ADC) is developed in an 0.18-/spl mu/m SiGe BiCMOS that supports sampling rates of 10 Gsample/s. The ADC is optimized to operate in digital equalizers for 10-Gb/s optical receivers, where the ADC has to deliver over three effective number of bits (ENOBs) at Nyquist. A fully differential flash ADC incorporating a wide-band track-and-hold amplifier (THA), a differential resistive ladder, an interpolation technique, and a high-speed comparator design is derived to resolve the aperture jitter and metastability error. The ADC achieves better than 4.1 effective bits for lower input frequencies and three effective bits for Nyquist input at 10 GS/s. The ADC dissipates about 3.6 W at the maximum clock rate of 10 GS/s while operating from dual -3.7/-3V supplies and occupies 3/spl times/3mm/sup 2/ of chip area.     

4- and 6-GS/s 4-bit frequency-translating hybrid ADCs in 90-nm CMOS

Two frequency-translating hybrid analog-to-digital converters (FTH-ADCs) are implemented using building blocks that are designed and fabricated in a 90-nm CMOS technology. These blocks include a mixer, a filter, and an ADC that are cascaded to build each analog processing path of the FTH-ADC. The mixer-filter path is designed with sufficient linearity and signal-to-noise-and-distortion ratio (SNDR) to accommodate for the desired resolution of the path ADC. A 4-bit flash ADC structure is used in each path. This path has a signal bandwidth of 0.5 GHz and frequency-translates the input signal into baseband and digitizes it with the sample rate of 2 GHz. Multiple such mixer-filter-ADC paths are then combined together with proper mixing frequencies in order to implement two- and three-channel ADC systems. The two- and three-channel systems have overall input bandwidths of 2 and 3 GHz and effective conversion rates of 4 and 6 GS/s, respectively, while maintaining their single-path resolution across their entire input bandwidths. The implemented architecture provides an extendible solution to improve the speed of ADCs by incorporating them in an FTH-ADC architecture.     

0.13 μm CMOS 60 dB SFDR的8 bit 250 MS/s模数转换器

论述了一种高速度低功耗的8位250 MHz采样速度的流水线型模数转换器(ADC).在高速度采样下为了实现大的有效输入带宽,该模数转换器的前端采用了一个采样保持放大器(THA).为了实现低功耗,每一级的运放功耗在设计过程中具体优化,并在流水线上逐级递减.在250 MHz采样速度下,测试结果表明,在1.2 V供电电压下,所有模块总功耗为60 mw.在19 MHz的输入频率下,SFDR达到60.1 dB,SNDR为46.6 dB,有效比特数7.45.有效输入带宽大于70 MHz.该ADC采用TSMC 0.13μm CMOS 1P6M工艺实现,芯片面积为800 μm×700μm.     

Photonic Bandwidth Compression Front End for Digital Oscilloscopes

Time-stretch photonic analog-to-digital converter (ADC) technology is used to make an optical front end that compresses radio-frequency (RF) bandwidth before input to a digital oscilloscope. To operate a time-stretch ADC in a continuous-time mode for bandwidth compression, the optical signal on which the RF is modulated must be segmented and demultiplexed. We demonstrate both spectral and temporal methods for overlapping the channels. Using the temporal method, we obtain a compression ratio of 3 with four channels. Mating this optical front end with a state-of-the-art four-channel digital oscilloscope with an input bandwidth of 16 GHz and a sampling rate of 50 GS/s gives a digitizer with 150 GS/s and an input bandwidth of 48 GHz. We digitize RF signals up to 45 GHz and obtain effective number of bits (ENOB) ~ 2.8 with single channels and ~ 2.5 with multiple channels, both measured over the 48-GHz instantaneous bandwidth of our system.     

一种采用砷化镓pHEMT工艺的超宽带DC-40GHz 4位单片数字衰减器

介绍了一种超宽带DC-40GHz的4位单片数字衰减器。该衰减器采用0.25μm砷化镓pHEMT工艺制造。据我所知,这种衰减器是至今国内文献报道中带宽最宽的。它通过采用适当的结构来得到超宽的带宽、低插入损耗以及高衰减精度。该衰减器具有1 dB的衰减步进和15 dB的衰减动态范围,插入损耗在40 GHz时小于5 dB,全衰减态及全频带内的输入输出回波损耗大于12 dB。     

A DC-4-GHz true logarithmic amplifier: theory and implementation

A 40 dB dynamic range, DC-4 GHz parallel-summation logarithmic amplifier is presented in this paper. The amplifier realizes a piecewise approximation to an exact logarithmic response. A design procedure that yields breakpoints on the exact response is described, along with delay-matching networks for parallel-summation logarithmic amplifiers. The amplifier was constructed in a 35 GHz silicon bipolar process, has /spl plusmn/5 dB logarithmic conformity over a DC-4 GHz bandwidth and has rise and fall times of 100 ps. The integrated circuit has dimensions of 2/spl times/2 mm/sup 2/ and consumes 750 mW from a -5 V supply.     

GaAs HBT wideband matrix distributed and Darlington feedbackamplifiers to 24 GHz

The designs and performances of a 2-24 GHz distributed matrix amplifier and 1-20 GHz 2-stage Darlington coupled amplifier based on an advanced HBT MBE profile that increases the bandwidth response of the distributed and Darlington amplifiers by providing lower base-emitter and collector-base capacitances are presented. The matrix amplifier has a 9.5 dB nominal gain and a 3-dB bandwidth to 24 GHz. This result benchmarks the highest bandwidth reported for an HBT distributed amplifier. The input and output VSWRs are less than 1.5:1 and 2.0:1, respectively. The total power consumed is less than 60 mW. The chip size measures 2.5×2.6 mm². The 2-stage Darlington amplifier has 7 dB gain and 3-dB bandwidth beyond 20 GHz. The input and output VSWRs are less than 1.5:1 and 2.3:1, respectively. This amplifier consumes 380 mW of power and has a chip size of 1.66×1.05 mm²      

一种数字CMOS工艺制造的10位100MS/s流水线ADC

介绍了采用0.18μm数字工艺制造、工作在3.3V下、10位100MS/s转换速率的流水线模数转换器。提出了一种适用于1.5位MDAC的新的金属电容结构,并且使用了高带宽低功耗运算放大器、对称自举开关和体切换的PMOS开关来提高电路性能。芯片已经通过流片验证,版图面积为1.35mm×0.99mm,功耗为175mW。14.7MS/s转换速率下测得的DNL和INL分别为0.2LSB和0.45LSB,100MS/s转换速率下测得的DNL和INL分别为1LSB和2.7LSB,SINAD为49.4dB,SFDR为66.8dB。     

A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS

A time-interleaved ADC is presented with 16 channels, each consisting of a track-and-hold (T&H) and two successive approximation (SA) ADCs in a pipeline configuration to combine a high sample rate with good power efficiency. The single-sided overrange architecture achieves a 25% higher power efficiency of the SA-ADC compared with the conventional overrange architecture, and look-ahead logic is used to minimize logic delay in the SA-ADC. For the T&H, three techniques are presented enabling a high bandwidth and linearity and good timing alignment. Single channel performance of the ADC is 6.9 ENOB at an input frequency of 4 GHz. Multichannel performance is 7.7 ENOB at 1.35 GS/s with an ERBW of 1 GHz. The FoM of the complete ADC including T&H is 0.6 pJ per conversion step. An improved version is presented as well and achieves an SNDR of 8.6 ENOB for low sample rates, and, with increased supply voltage, it reaches a sample rate of 1.8 GS/s with 7.9 ENOB at low input frequencies and an ERBW of 1 GHz. At fin = 3.6 GHz, the SNDR is still 6.5 ENOB, and total timing error including jitter is 0.4 ps rms.     

A 1.4-V 25-Mw 600-MS/s 6-bit folding and interpolating ADC in 0.13-μm CMOS

A 600-MSample/s 6-bit folding and interpolating analog-to-digital converter (ADC) is presented. This ADC with single track-and-hold (T/H) circuits is based on cascaded folding amplifiers and input-connection-improved active interpolating amplifiers. The prototype ADC achieves 5.55 bits of the effective number of bits (ENOB) and 47.84 dB of the spurious free dynamic range (SFDR) at 10-MHz input and 4.3 bit of ENOB and 35.65 dB of SFDR at 200-MHz input with a 500 MS/s sampling rate; it achieves 5.48 bit of ENOB and 43.52 dB of SFDR at 1-MHz input and 4.66 bit of ENOB and 39.56 dB of SFDR at 30. 1-MHz input with a 600-MS/s sampling rate. This ADC has a total power consumption of 25 mW from a 1.4 V supply voltage and occupies 0.17 mm~2 in the 0.13-μm CMOS process.     

12 Gb/s GaAs PHEMT跨阻抗前置放大器

采用0.5 μ m GaAs PHEMT工艺研制了一种单电源偏置光接收机跨阻抗前置放大器.放大器-3dB带宽约为9.5GHz;在50MHz~7.5GHz范围内,跨阻增益为43.5±1.5dB Ω ,输入输出回波损耗均小于-10dB;带内噪声系数在4dB~6.5dB之间,由此得到的最小等效输入噪声电流密度约为17.6pA/ Hz ;输入12Gb/s NRI伪随机序列时,放大器输出眼图清晰,眼开良好.     

一种二极管桥式跟踪保持电路设计

设计了一种基于二极管桥的两级全差分跟踪保持电路,两级模块由独立的时钟控制,可以各自工作在跟踪模式。芯片采用1μm GaAs HBT工艺实现,芯片大小为1.8mm×2mm,功耗2.75W。经测试,电路可以工作在1GS/s采样速率下,单端输入峰峰值250mV信号时采样带宽超过7GHz;单端输入峰峰值250mV,DC-2GHz信号时,电路具有8bit有效位。     

A 6-Bit 1.6-GS/s Low-Power Wideband Flash ADC Converter in 0.13-$mu$ m CMOS Technology

In this work, a new termination technique for the averaging network of the flash analog-to-digital converter (ADC) input preamplifiers is devised. The proposed technique eliminates the over-range voltage headroom consumed by the dummy preamplifiers and therefore, the input capacitance and power dissipation of the ADC is reduced. This technique is applied to the design of a 6-bit 1.6-GS/s flash ADC in 0.13-$mu$ m CMOS technology. The measured peak INL and DNL are 0.42 LSB and 0.49 LSB, respectively. The ADC achieves an effective resolution bandwidth (ERBW) of 800 MHz and an SNDR of 30 dB at 1.45-GHz input signal frequency while consuming 180 mW.      

26GS/s单bit量化降速芯片

基于1μm GaAs HBT工艺设计并实现了一种26GS/s单bit量化降速芯片。芯片采用树形级联架构,集成前端宽带比较器,综合优化各级降速单元拓扑,在功耗、速度各方面达到最优化。测试结果表明,芯片在26GS/s转换速率下,其SFDR大于8dBc,数据带宽达13GHz,显示出其在电子对抗及高速数据处理方面的潜力。