基于HV-CMOS工艺集成PIN光敏元的CMOS传感器设计

PIN光电二极管相对于pn结型光电二极管具有结电容小、量子效率高等优点,但采用标准低压CMOS(LV-CMOS)工艺研制的CMOS传感器只能实现基于n阱/p衬底的pn结光敏元与片上电路的集成,高压CMOS(HV-CMOS)工艺的发展为CMOS电路与PIN光敏元列阵的单片集成提供了可能。基于HV-CMOS工艺设计了一种集成PIN光敏元列阵的CMOS传感器,并对器件的光电响应进行了测试评估。结果表明,集成PIN光敏元的CMOS传感器具有更高的像素增益和量子效率,而暗电流、输出摆幅、线性度等特性保持良好。在500~900nm宽波段范围内,器件的量子效率均达到80%以上,在950nm附近的量子效率达到25%,优于采用其他工艺制作的CMOS传感器。     

等离子平板显示选址芯片设计

采用标准CMOS工艺设计出PDP(Plasma Display Panel)选址芯片，重点设计出一种高压结构-HV—CMOS(High Voltage CMOS)结构，采用单阱非外延工艺以降低生产难度和成本，实现了高低压之间的兼容。同时采用TSLIPREM-4对该结构进行工艺模拟、并用MEDICl分析其电流-电压和击穿等特性，说明该结构可以满足设计要求。     

一种基于标准CMOS工艺的单片光互连

探索了采用标准CMOS工艺实现单片光互连的可行性。采用特许(Chartered)半导体公司3.3V、0.35μm标准模拟CMOS工艺设计并制造了一种单片光互连系统,并用两种结构研究了衬底噪声耦合对互连性能的影响。测试结果表明:该光互连系统可工作于几×103Hz,验证了基于标准CMOS工艺的单片光互连系统是可行的。     

适用于笔记本电脑的高性能CMOS LVDS驱动器的设计

提出了一种适用于笔记本电脑平板显示嚣接口的高性能CMOS LVDS(Low Voltage Differential Signaling)驱动器的设计方法。用高性能CMOS LVDS驱动器作I／O接口单元是减小当前CMOS工艺芯片内外速度差异的重要手段。文章着重分析了高性能CMOS LVDS驱动器的电路结构及其工作原理，采用TSMC的0．25μm CMOS工艺模型，在Cadence环境下用Spectre仿真器进行模拟，给出了该驱动器的仿真结果。     

一种采用CMOS0.18μm制造的带EBG结构小型化的片上天线

采用标准0.18μm CMOS工艺设计制造了一种带EBG(电磁带隙)结构的小型化片上天线。该片上天线由一根长1.6mm的偶极子天线以及一对一维的尺寸为240μm×340μmEBG结构构成。分别对该EBG结构以及片上天线的S11及S21进行了仿真和测试,结果表明该片上天线工作在20GHz,具有小型化的性能,同时具备三次谐波抑制的功能。     

与CMOS工艺兼容的硅高速光电探测器模拟与设计

用器件模拟的方法,设计了一种与常规CMOS 工艺兼容的硅高速光电探测器,该探测器可与CMOS接收机电路单片集成,对该探测器进行了器件模拟研究,给出了该探测器的电路模型.通过MOSIS(MOS implementation support project) 0.35μm COMS工艺制做了该探测器,实际测试了该器件的频率响应和波长响应,探测器频率响应在1GHz以上,峰值波长响应在0.69μm.     

CMOS工艺中横向双极型晶体管的直流与交流电学特性

在 CMOS工艺结构中,将位于阱中的 MOS 器件加适当的偏置,可以使其变为体内器件、以横向双极管的模式工作.本文利用 3μm P-well和 2μm N-well两种 CMOS工艺设计了这种横向双极器件,分析讨论了这种器件的工作原理和特点,并给出其典型的直流和交流参数的实验数据.这些分析和实验数据将有助于电路设计者了解和掌握该器件的电流、频率工作范围及特性,以便在CMOS电路中充分发挥其特长.     

与CMOS工艺兼容的硅高速光电探测器模拟与设计

用器件模拟的方法,设计了一种与常规CMOS 工艺兼容的硅高速光电探测器,该探测器可与CMOS接收机电路单片集成,对该探测器进行了器件模拟研究,给出了该探测器的电路模型.通过MOSIS(MOS implementation support project) 0.35μm COMS工艺制做了该探测器,实际测试了该器件的频率响应和波长响应,探测器频率响应在1GHz以上,峰值波长响应在0.69μm.     

一种基于0.18μm CMOS工艺的上电复位电路

介绍了一种采用0.18μm CMOS工艺制作的上电复位电路。为了满足低电源电压的设计要求,采用低阈值电压(约0V)NMOS管和设计的电路结构,获得了合适的复位电压点;利用反馈结构加速充电,提高了复位信号的陡峭度;利用施密特触发器,增加了电路的迟滞效果。电路全部采用MOS管设计,大大缩小了版图面积。该上电复位电路用于一种数模混合信号芯片,采用0.18μm CMOS工艺进行流片。芯片样品电路测试表明,该上电复位电路工作状态正常。     

基于电流镜积分的红外探测器读出电路设计

详细分析了电流镜积分(CMI)读出电路的工作原理、设计过程和CMI结构的噪声,并用CSMC 0.5μm CMOS工艺对所设计的电路进行仿真和版图设计,仿真结果表明CMI结构在电源电压为5 V,积分电容为2 pF时能提供一个较大的电荷存储能力(6.25x107个电子);在光生电流为50 pA时,探测器偏压稳定在3.615...     

Evolution of a CMOS Based Lateral High Voltage Technology Concept

This work describes the evolution of a CMOS based lateral high voltage (HV) technology concept, where the HV part is integrated in a low voltage (LV) CMOS technology. The starting point is an existing substrate related state of the art 0.35 μm LV CMOS technology (C35) which is optimized for digital and analog applications. The technology covers two different gate oxide thicknesses which allow to control two LV logic levels with different gate voltages and drain voltages (max.V_GS=max.V_DS=3.3V, max.V_GS=max.V_DS=5.5 V). The key requirement for the HV integration is to preserve the LV design rules (DR) and the LV transistor parameters. Only in this case it is possible to reuse the digital and analog intellectual property (IP) blocks. The major challenge of this integration is to overcome the relatively high surface concentration of the 0.35 μm CMOS process which defines the threshold voltages and the short channel effects. Because the HV devices use the same channel formation like the LV devices, a process concept for the drift region connection to the channel is the key point in this integration approach. A benchmark for the process complexity is given by the mask count (low volume production) and the number of alignments (high volume production). Starting from a very simple approach n-channel HV transistors are described which can be integrated in the substrate related LV CMOS concept without adding additional masks. During the next steps the LV CMOS process is modified continuously using additional masks and alignment steps. From each step to step the new HV properties are explained and the trade-off between process complexity and device performance is discussed.     

Scalable High Voltage CMOS technology for Smart Power and sensor applications

Summary  Integration of low voltage analog and logic circuits as well as high-voltage (HV) devices for operation at greater than 5 V enables Smart Power ICs used in almost any system that contains electronics. HVCMOS (High-Voltage CMOS) technologies offer much lower process cost, if compared to BCD technologies, they enable multiple HV levels on a single chip, and need less effort when scaling to smaller CMOS technology nodes or when integrating embedded non-volatile memory. In this work we propose a new 0.35 μm HVCMOS technology that can overcome the previous limitations in drive currents. It can match the low HV chip sizes (Rdson) of typical BCD processes while maintaining the low process complexity with only 2 mask level adders on top of CMOS. We also introduce a figure of merit (FOM) for comparing HV technologies. Key elements of making this newly proposed 0.35 μm HVCMOS so competitive to BCD technologies are discussed and a device lifetime of more than 10 years, operating temperatures of 150 °C and ESD robustness of 4 kV HBM and higher, as well as the integration of a highly robust embedded EEPROM/Flash technology is shown. We also provide first verification results of the scalability of the proposed 0.35 μm HVCMOS technology to 0.18 μm and beyond as well as to currents of up to 8 A.      

System integration of high voltage electrostatic MEMS actuators

A system integration for High Voltage (HV) electrostatic MicroElectroMechanical Systems (MEMS) actuators is introduced on a micro-Printed Circuit Board. The system includes a programmable microcontroller, a programmable DC/DC converter, a multi output HV interface and electrostatic MEMS actuators. The system produces high output voltages (10–300 V) and can control a large variety of MEMS capacitive loads (1 to 50 pF) by combining diverse semiconductor technologies. This system proves that technologies, such as low voltage CMOS of different processes, high voltage DMOS and MEMS, can interact, communicate and even be integrated as a System In Package (SIP), providing significant size and cost reductions. The system was programmed to control electrostatic MEMS actuator. The DC/DC converter was made from components of different technologies and two addressable high voltage CMOS interfaces were fabricated with DALSA's 0.8 μm High Voltage process. A prototype of the global system has been built and tested.     

A standard CMOS high-voltage transmitter for ultrasound medical imaging applications

A high-voltage (HV) transmitter for ultrasound medical imaging applications is designed using 0.18-µm CMOS (complementary metal oxide semiconductor) technology. The proposed HV transmitter achieves high integration by employing standard CMOS transistors in a stacked configuration with dynamic gate biasing circuit while successfully driving the capacitive output load with an HV pulse without device breakdown reliability issues. The HV transmitter, which includes the output driver and voltage level-shifters, generates up to 30-Vp-p pulses at 1.25 MHz frequency and occupies 0.035 mm² of layout area.     

CMOS PWM D类音频功率放大器的过流保护电路

基于Class-D音频功率放大器的应用,采用失调比较器及单边迟滞技术,提出了一种过流保护电路,其核心为两个CMOS失调比较器。整个电路基于CSMC0.5μmCMOS工艺的BSIM3V3Spice典型模型,采用Hspice对比较器的特性进行了仿真。失调比较器的直流开环增益约为95dB,失调电压分别为0.25V和0.286V。仿真和测试结果显示,当音频放大器输出短路或输出短接电源时,过流保护电路都能正常启动,保证音频放大器不会受到损坏,能完全满足D类音频放大器的设计要求。过流保护电路有效面积为291μm×59.5μm。     

Integration challenges in sub-0.25 μm CMOS-based technologies

Market demands, which require increased functionality at lower costs are driving the development of high performance CMOS technologies with very high integration density. These demands are pushing the continuous scaling down of technologies and are resulting in a progressive acceleration of the rate of introduction of new technology generations.Current research and development activities in CMOS technology are focused on scaling CMOS technologies below 0.25 μm dimensions. While some of the process modules can be scaled down in a conventional way, in some cases severe limitations are reached and it is necessary to introduce major modifications to the process flow.In this paper we will present an overview of the main considerations to be kept in mind when scaling down to a 0.18 or 0.13 μm CMOS technology generation.     

一种10-ppm/~oC低压CMOS带隙电压基准源设计

在对传统CMOS带隙电压基准源电路分析和总结的基础上,综合一级温度补偿、电流反馈和电阻二次分压技术,提出了一种10-ppm/oC低压CMOS带隙电压基准源。采用差分放大器作为基准源的负反馈运放,简化了电路的设计,放大器的输出用于产生自身的电流源偏置,提高了电源抑制比(PSRR)。整个电路采用TSMC 0.35mm CMOS工艺实现,采用Hspice进行仿真,仿真结果证明了基准源具有低温度系数和高电源抑制比。     

Impact of technology scaling and process variations on RF CMOS devices

Inspired by the huge improvement in the RF properties of CMOS devices, RF designers are invading the wireless market with all-CMOS RF transceivers and system-on-chip implementations. In this work, the impact of technology scaling on the RF properties of CMOS; frequency properties, noise performance, linearity, stability, and non-quasi static effects is investigated to provide RF designers with an insight to the capabilities of future CMOS technologies. Moreover, the RF frequency performance of CMOS is investigated under the influence of process variations for different CMOS generations. Using the BSIM4 model, it is found that future CMOS technologies have high prospects in the RF industry and will continue challenging other technologies in the RF domain to be the dominant technology for RF transceivers and system-on-chip implementations.     

一种应用于低压CMOS差分放大器的失调取消技术

基于对CMOS差分放大器的非线性和元件失配理解的基础上,提出了一种应用于低电压CMOS差分放大器的失调取消技术.这种技术在不需要增加功耗的基础上,通过把输出端的失调电压转移到差分放大器的其他节点,从而达到减小输入参考的失调电压的目的.为了验证这种技术,设计了一个工作电压为1.8V的低失调的CMOS差分放大器.仿真结果表明,在负载晶体管的失配为20%,输入放大管的失配为10%时,利用这种失调转移技术,输入参考的失调可以减少40%.同已发表的失调取消技术相比,利用这种技术可以达到更低的功耗和更高的集成度.     

双等比CMOS缓冲器的设计

双比CMOS缓冲器可分为双等比和双变比CMOS缓冲器，文章对双等比CMOS缓冲器进行了设计研究，提出了它的一种次优实验方法，双等比CMOS缓冲器容易取得对称的传播延迟，可以在较小的面积与功耗下取得和等比CMOS缓冲器相等的传播延迟，使用0．35um工艺参数的HSPICE模拟结果证实了双等比CMOS缓冲器的性能。