新一代运载火箭时序仿真系统信号完整性分析

新一代运载火箭时序仿真系统具有数字电路速度快、集成度高的特点,系统要求发出多路高精度时序、时串信号以满足新一代运载火箭地面测试设备的检查与校准需求,因此信号完整性问题在系统设计中不容忽视。针对仿真系统的典型模块(USB 3.0 Super-speed差分线、FPGA外设数据走线、时钟走线)进行建模分析仿真得出PCB硬件电路设计参数,给出时序仿真系统设计信号完整性问题的抑制和解决方法,优化了板级信号质量,改善系统可靠性、工作连续性和输出精度,可有效提高新一代运载火箭测试效率和测试可靠性。

Analysis on Signal Integrity of New Generation Launch Vehicle Timing Simulation System

The new generation Launch vehicle has the features of high-speed and high-density like any other digital circuit. Multi-channel, high-precision timing sequence and timing bunchs are required to meet the new generation launch vehicle ground test equipment demands of test and calibration, so the problem of signal intergrity can not be ignored during its designing. Parameters of PCB circuit can be obtained to restrain and solve the problem of signal intergrity by modeling and analysising the typical models (USB 3.0 Super-speed Differential pairs, routing of digital and clock of the FPGA peripherals). Design system with these parameters can optimize the quality of signals on the PCB board. Reliability, work continuity and outputing precision of the system can be enhanced, it alse improve the test efficiency and test reliability of the new generation launch vehicle.