Multiple-tapped-delay-line hardware-linearisation technique based on wire load regulation

This article describes designing, implementation and tuning processes of multiple-tapped-delay-line (MTDL). Obtained MTDL can be implemented in various field-programmable-logic-devices (FPGA) devices and applied for time-to-digital-converters (TDC) construction. The task of tuning process is the tapped-delay-line (TDL) linearisation, and consists of two stages. The first stage depends on selecting an appropriate configurable-logic-block (CLB) for particular delay-segment realization and selecting proper connection between these blocks. The second tuning stage, that is essential from this article viewpoint, depends on inter CLBs connecting wires delay regulation realized directly by load regulation. The Load regulation depends on connecting an appropriate number of unused three-state-buffers or CLB inputs to the wire which delay is adjusted. Depending on the number of inputs connected to the wire its capacitance changes that influences its time-constant and finally changes its time-delay.The MTDL mathematical model, obtained characteristics and results of time-interval (TI) measurements are also presented. The derived TDL model provides information about how the particular wire delay should be changed and in which order the changes should be executed. This makes the designing process predictable and easy to carry out. Presented characteristics confirm the proper operation of presented linearisation technique. The proper operation of the whole measuring module is confirmed by obtained TIs histograms presentation.