基于EDA技术的图像边缘检测协处理器的设计

在嵌入式图形系统处理领域,图像处理的速度问题一直是一个很难突破的设计瓶颈.文章在介绍一种全新的DSP CPLD图像处理系统工作原理的基础上,阐述了一个基于EDA技术的、用FPGA实现的800×600像素的图像边缘检测协处理器的设计,包括边缘检测算法选择、系统的FPGA实现设计和有关仿真结果等.该协处理器的像素处理方式采用全硬件并行及流水线技术,比单独采用单片机和DSP的系统,其处理速度分别提高了400倍和10倍,同时该系统集成在一块集成芯片上,体积小,功耗低,可靠性高,并可现场编程,在线升级.

The Design of Image Edge Detection Co-processor Based on EDA

The speed of image processing is a key problem. The design of the image edge detection co-processor based on EDA techniques was illustrated. In this image process system, new architecture was used (DSP+CPLD). The discussion included the image edge detection algorithm selection, the system implementation design and the simulation result. The new techniques such as hardware parallel processing technique and streamline technique were introduced. Comparing with single MCU or DSP application system, this new architecture enhances the system speed by 400 and 10 times. This system gathers on a chip, the physical volume is smaller, the power consume is lower, the reliability is higher, programmable, and can be upgraded on-line.