| 高性能异或门电路的设计 |
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| 引用本文： | 董艳燕,韦一,陈君.高性能异或门电路的设计[J].中国计量学院学报,2012,23(4):383-387. |
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| 作者姓名： | 董艳燕 韦一 陈君 |
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| 作者单位： | 中国计量学院光学与电子科技学院,浙江杭州,310018 |
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| 摘 要： | 在分析已发表的典型异或门电路的基础上,提出一种新型高性能的异或门电路,其电路核心部分仅3个晶体管,包括一个改进型互补CMOS反相器和一个NMOS传输门.在TSMC0.18μm CMOS工艺下经HSPICE模拟.结果表明,与已有的异或门电路相比,新设计在速度和功耗延迟积上具有较大的优势.
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| 关 键 词： | 异或门 CMOS反相器 传输门 |
Design of a novel high performance XOR gate |
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| DONG Yan-yan
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WEI Yi
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CHEN Jun.Design of a novel high performance XOR gate[J].Journal of China Jiliang University,2012,23(4):383-387. |
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| Authors: | DONG Yan-yan WEI Yi CHEN Jun |
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| Affiliation: | (College of Optical and Electronic Technology,China Jiliang University,Hangzhou 310018,China) |
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| Abstract: | Based on the analysis of published XOR gate circuits,a novel design of XOR gate was proposed.The key circuit of the proposed XOR gate uses only three transistors which induded a modified version of complementary CMOS inverter and a NMOS pass transistor logic.HSPICE simulation showed that the proposed design of XOR gate has significant advantages in speed and PDP under the TSMC 0.18 μm CMOS technology,as compared to the existing XOR gate circuits. |
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| Keywords: | XNOR gate CMOS inverter transmission |
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