BIST design for detecting multiple stuck-open faults in CMOS circuits using transition count

This paper presents a built-in self-test (BIST) scheme for detecting all robustly testable multiple stuck-open faults confined to any single complex cell of a CMOS circuit. The test pattern generator (TPG) generates alln·2 ⁿ single-input-change (SIC) ordered test pairs for ann-input circuit-under-test (CUT) contained in a sequence of length 2n·2 ⁿ . The proposed design is universal, i.e., independent of the structure and functionality of the CUT. A counter that counts the number of alternate transitions at the output of the CUT, is used as a signature analyzer (SA). The design of TPG and SA is simple and no special design-or synthesis-for-testability techniques and/or additional control lines are needed. Hafizur Rahman received his Bachelor degree in electrical engineering from the University of Calcutta, India in 1986, Master degree in electrical engineering from the Jadavpur University, India in 1988. He is at present on the faculty of the Indian Institute of Information Technology, Calcutta, India. His research interests include VLSI testing and logic synthesis. Debesh K. Das received his Bachelor and Master degrees in, electronics and telecommunication engineering and the Ph.D. degree in computer science and engineering from the Jadavpur University, India in 1982, 1984, and 1997 respectively. His research interests include VLSI testing and logic synthesis. Bhargab B. Bhattacharya received the B.Sc. degree in physics from the Presidency College, Calcutta, India, in 1971, the B.Tech. and M.Tech. degrees in radiophysics and electronics, and the Ph.D. degree in computer science all from the University of Calcutta in 1974, 1976, and 1986 respectively. Since 1982, he has been on the faculty of the Indian Statistical Institute, Calcutta, where he became full professor in 1991. As a visiting professor, he had been with the Department of Computer Science and Engineering, University of Nebraska-Lincoln, USA, during 1985–1987, and 2001–2002. In the summers of 1998, 1999, and 2000, he visited the Fault-Tolerant Computing Group, Institute of Informatics at the University of Potsdam, Germany. His research interests include logic synthesis and testing of VLSI circuits, graph algorithms, and image processing. He has published more than 100 papers in archival journals and refereed conference proceedings. Currently, he is collaborating with Intel Corporation, USA and IRISA, France, for development of image processing hardware, and reconfigurable parallel computing tools. Dr. Bhattacharya is a Fellow of the Indian National Academy of Engineering. He served on the conference committees of the International Test Conference (ITC), the Asian Test Symposium (ATS), the VLSI Design and Test Workshop (VDAT), the International Conference on Advanced Computing (ADCOMP), and the International Conference on High-Performance Computing (HiPC). For the International Conference on VLSI Design, he served as Tutorial Co-Chair in 1994, as Program Co-Chair in 1997, and as General Co-Chair in 2000.