基于VERILOG-HDL的简化异步收发器的设计与仿真

该文阐述了通用异步收发器(UART)异步串行通信原理,介绍了实现UART异步串行通信的硬件接口电路及各部分硬件模块。该文基于Verilog语言实现了接收器和发送器这两个UART的内部核心功能模块,通过Modelsim对相应Verilog-HDL程序的仿真,验证了其异步串行数字接收和发送的功能。

Design and Simulation of Universal Asynchronous Receiver/transmitter Based on Verilog-HDL

The paper expatiate the asynchronous serial communication theory of the UART,introduce the hardware interface circuit ofasynchronous serial communication and the hardware module of each part. By using the Verilog-HDL ,the article realize the transmitterand receiver,which are kernel functional modules of the UART. Through the Modelism simulation,we validate the function of asyn-chronous serial receiver and transmitter.