基于ARM+FPGA平台的二值神经网络加速方法研究

现有的卷积神经网络由于其结构复杂且依赖的数据集庞大，难以满足某些实际应用或者计算平台对运算性能的要求和能耗的限制。针对这些应用或计算平台，对基于ARM+FPGA平台的二值化算法进行了研究，并设计了二值神经网络，该网络减少了数据对存储单元的需求量，也降低了运算的复杂度。在ARM+FPGA平台内部实现时，通过将卷积的乘累加运算转换为XNOR逻辑运算和popcount等操作，提高了整体的运算效率，降低了对能源和资源的消耗。同时，根据二值神经网络中数据存储的特点提出了新的行处理改进算法，提高了网络的吞吐量。该实现方式在GOPS、能源和资源效率方面均优于现有的FPGA神经网络加速方法。

Research of binary neural network acceleration method based on ARM+FPGA platform

The existing convolutional neural network(CNN) has complicated structure and bases on huge dataset, so it is difficult to meet the requirement of computing performance and limitation of energy consumption in some practical applications or computing platforms. Aiming at these applications or platforms, this paper studied the binary algorithm based on ARM+FPGA platform and designed a binary neural network(BNN). It reduced the demand for data storage units and simplified the computational complexity. When implemented in the ARM+FPGA platform, it converted the convolution multiply-accumulate operation into XNOR logic and popcount operation, which improved the overall operation efficiency and declined the consumption of energy and resources. At the same time, based on the characteristics of data storage in BNN, this paper proposed a new row-processing algorithm to improve the throughput of the network. In a word, this implementation is superior to the existing FPGA neural network acceleration methods in terms of GOPS, energy and resource efficiency.