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一种基于沙漏网络的多层次协同搜索方法
引用本文:陈桂荣,粟涛.一种基于沙漏网络的多层次协同搜索方法[J].计算机应用研究,2022,39(8).
作者姓名:陈桂荣  粟涛
作者单位:中山大学电子与信息工程学院,中山大学电子与信息工程学院
基金项目:广东省重大科技计划资助项目(2021B110127007,2019B010140002)
摘    要:目前,人工智能快速发展,人们可以通过探索硬件设计空间使优秀的神经网络算法高效部署在FPGA加速器。然而,由于参数量大、操作过于复杂而导致算法与硬件难以匹配,加速效率不高。为了算法和硬件两者匹配性更强,提出了一种多层次协同搜索的方法,采用SPOS搜索策略并以检测准确率和延时为评估目标,搜索出最优神经网络架构、量化方式和硬件设计参数组合。该方法应用在姿态识别中具有优异性能的沙漏网络中,在获取候选子网络量化前、后的检测准确率的同时对硬件设计参数使用遍历搜索得到预估延时,根据目标函数获取最高得分的最优组合。为了保证获取的数据有效性,子网络需要进行重新训练、量化后重新推理得到检测准确率,获取硬件设计参数则利用基于Spinal HDL设计的加速器模板进行仿真测试得到测试延时。就平均而言,该方法比文献[1]减少了83.3%的参数,准确率只下降了0.69;比传统加速方法平均减少了33.2%参数量,准确率只下降了0.46,网络推理的测试总延时减少22.1%,在沙漏块的测试延时减少67.8%。总体而言,该协同搜索方法对于沙漏网络的优化有一定效果,比传统加速设计方法更有优势。

关 键 词:神经网络    FPGA    协同搜索    沙漏网络    延时模型
收稿时间:2022/1/21 0:00:00
修稿时间:2022/7/18 0:00:00

Multi-level co-exploration method based on hourglass network
Chen Guirong and Su Tao.Multi-level co-exploration method based on hourglass network[J].Application Research of Computers,2022,39(8).
Authors:Chen Guirong and Su Tao
Affiliation:School of Electronics and Information Technology ,Sun Yat-Sen University,
Abstract:At present, with the rapid development of AI, people can efficiently deploy excellent neural network algorithms on FPGA accelerators by exploring the hardware design space. However, due to the large amount of parameters and complex operation, it is difficult to match the algorithm with the hardware, and the acceleration efficiency is low. In order to better match the algorithm and hardware, this paper proposed a multi-level co-exploration method, adopted SPOS search strategy, aimed at accuracy and latency, to obtain the optimal neural network architecture, quantization method and hardware design combination. It applied the method to hourglass network which have high accuracy in pose estimation. While obtained the accuracy before and after quantization of candidate sub networks, it used traversal method to search hardware design parameters and obtain the estimated latency, and then got the optimal combination with the highest score according to the target function. In order to ensure the effectiveness of the obtained data, it retrained the sub network, then quantified and inferenced again to obtain the accuracy. It simulated the obtained hardware design parameters to get the testing latency, using the accelerator template designed based on Spinal HDL. On average, co-exploration method reduced the parameters by 83.3% and with only 0.69 accuracy loss compared with the original structure; reduced the parameters by 33.2%, with only 0.46 accuracy loss, reduced the total testing latency of network inference by 22.1% and reduced the testing latency in hourglass block by 67.8% compared with the traditional acceleration method. Overall, the proposed co-exploration method has a certain effect on the optimization of hourglass network, and it has more advantages than the traditional acceleration method.
Keywords:neural network  FPGA  co-exploration  hourglass network  latency model
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