热安全约束下异构多核系统动态映射方法

异构多核平台通过集成不同类型的处理核来为系统设计提供灵活性，从而使应用程序可以根据自身需求动态地选择不同类型的处理核来进行处理，实现应用程序的高效运行。随着半导体技术的发展，单芯片上集成的核心数量随之增加，使得现代多核处理器具有更高的功率密度，而这会导致芯片温度的升高，最终会对系统性能造成一定的负面影响。为了充分发挥出异构多核处理系统的性能优势，提出一种在满足温度安全功率的前提下，以最大化系统性能为目标的动态映射方法。该方法考虑异构多核系统的两种异构指标来确定映射方案：第一种异构指标是核心类型，不同类型的处理核具有不同的特征，因而它们适用于处理不同的应用程序；第二种异构指标是热感受性，芯片上不同的处理核位置具有不同的热感受性，越是中心位置的处理核受到的来自于其他处理核的热传递越多，因而温度也就越高。为此，提出一种基于神经网络性能预测器来对线程与处理核类型进行匹配，并利用热安全功率（TSP）模型将经过匹配后的线程映射到芯片上的具体位置。实验结果表明，所提出的方法与常见的轮询调度（RRS）相比，能在保证热安全约束的前提下将平均每个时钟周期内程序所执行的指令数，即指令/周期（IPC）提高53%左右。

Dynamic mapping method for heterogeneous multi-core system under thermal safety constraint

The heterogeneous multi-core platform provides flexibility for system design by integrating different types of processing cores, so that applications can dynamically select different types of processing cores according to their requirements and realize efficient operation of applications. With the development of semiconductor technology, the number of integrated cores on a single chip has increased, making the modern multi-core processors have a higher power density, and this will cause the chip temperature to rise, which will eventually cause a certain negative impact on the system performance. To make the performance advantages of heterogeneous multi-core processing system fully utilized, a dynamic mapping method was proposed to maximize the performance of heterogeneous multi-core systems under the premise of satisfying temperature safe power. In this method, two heterogeneous indices of heterogeneous multi-core systems including core type and thermal susceptibility were considered to determine the mapping scheme:the first heterogeneous index is the core type. Different types of processing cores have different characteristics, so they are suitable for processing different applications. The second heterogeneous index is thermal susceptibility. Different processing core positions on the chip have different thermal susceptibility. The processing cores closer to the center receive more heat transfer from other processing cores, so that they have higher temperature. For the above, a neural network performance predictor was created to match threads to processing core types, and the Thermal Safe Power (TSP) model was used to map the matched threads to specific locations on the chip. Experimental results show that the proposed method achieves about 53% increase of the average number of instructions executed by the program in each clock cycle-Instruction Per Cycle (IPC) under the premise of ensuring thermal safety constraints compared with the common Round Robin Scheduler (RRS).