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RSA 踪迹驱动指令Cache 计时攻击研究
引用本文:陈财森,王韬,郭世泽,周平.RSA 踪迹驱动指令Cache 计时攻击研究[J].软件学报,2013,24(7):1683-1694.
作者姓名:陈财森  王韬  郭世泽  周平
作者单位:军械工程学院 信息工程系, 河北 石家庄 050003;装甲兵工程学院, 北京 100072;军械工程学院 信息工程系, 河北 石家庄 050003;北方电子设备研究所, 北京 100083;军械工程学院 信息工程系, 河北 石家庄 050003
基金项目:国家自然科学基金(60772082); 河北省自然科学基金(08M010)
摘    要:指令Cache 攻击是基于获取算法执行路径的一种旁路攻击方式.首先,通过分析原有RSA 指令Cache 计时攻击存在可行性不高且能够获取的幂指数位不足等局限性,建立了新的基于监视整个指令Cache 而不只是监视特定指令Cache 的踪迹驱动计时攻击模型;然后,提出了一种改进的基于SWE 算法窗口大小特征的幂指数分析算法;最后,在实际环境下,利用处理器的同步多线程能力确保间谍进程与密码进程能够同步运行.针对OpenSSLv.0.9.8f 中的RSA算法执行指令Cache 计时攻击实验,实验结果表明:新的攻击模型在实际攻击中具有更好的可操作性;改进的幂指数分析算法能够进一步缩小密钥搜索空间,提高了踪迹驱动指令Cache 计时攻击的有效性.对于一个512 位的幂指数,新的分析算法能够比原有分析算法多恢复出大约50 个比特位.

关 键 词:指令Cache  计时攻击  旁路攻击  RSA  密码算法  踪迹驱动  同步多线程
收稿时间:2011/5/31 0:00:00
修稿时间:2012/9/29 0:00:00

Research on Trace Drive Instruction Cache Timing Attack on RSA
CHEN Cai-Sen,WANG Tao,GUO Shi-Ze and ZHOU Ping.Research on Trace Drive Instruction Cache Timing Attack on RSA[J].Journal of Software,2013,24(7):1683-1694.
Authors:CHEN Cai-Sen  WANG Tao  GUO Shi-Ze and ZHOU Ping
Affiliation:Department of Information Engineering, Ordnance Engineering College, Shijiazhuang 050003, China;The Academy of Armored Forces Engineering, Beijing 100072, China;Department of Information Engineering, Ordnance Engineering College, Shijiazhuang 050003, China;The Institute of North Electronic Equipment, Beijing 100083, China;Department of Information Engineering, Ordnance Engineering College, Shijiazhuang 050003, China
Abstract:The I-cache timing attack which exploits the instruction path of a cipher is one type of side channel attack. First, by analyzing the complications in the previous I-cache timing attacks on RSA algorithm because of how hard it has been to put them into practice, and how the number of the inferred bits is insufficient, this paper builds a new trace driven I-cache timing attack model via spying on the whole I-cache, instead targeting the instruction cache to which the special function mapped. Next, an improved analysis algorithm of the exponent based on the characteristic of the side of window in sliding window exponentiation (SWE) algorithm is proposed. Finally, an I-cache timing attack is implemented on RSA of OpenSSL v.0.9.8f in a practical environment, using a simultaneous multithreading processor to insure that the spy process and the cipher process can run in parallel. Experimental results show that the proposed attack model has strong applicability in real environments; the improved analysis algorithm of the exponent can further reduce the search space of the bits of the key, and improve the effectively of the trace driven I-cache timing attack. For a 512-bit exponent, it can recover about 50 bits of exponent more than the previous.
Keywords:I-cache timing attack  side channel attack  RSA cryptographic algorithm  trace-driven  simultaneous-multithreading
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