基于Montgomery模乘的RSA加密处理器

提出一种基4的Montgomery模乘算法及优化的硬件结构，将传统基2模乘运算迭代次数减少近一半。在该模乘模块基础上设计高速RSA加密处理器，采用进位保留形式的全并行模幂运算流程，避免长进位链和中间结果转换的问题。结果表明，该设计同时适应FPGA和ASIC实现，完成一次标准1 024位RSA加密运算仅需9 836个周期，加密速率提高50%以上。

RSA Encryption Processor Based on Montgomery Modular Multiplication

A radix-4 Montgomery modular multiplication and the optimized circuit architecture are presented. It can reduce iterations of traditional radix-2 modular multiplication to about 50%. Based on this module, the implementation of high speed RSA encryption processor follows completely parallel modular exponentiation flow with Carry Save Addition(CSA) structure to perform long integer arithmetic. This avoids the repeated interim output/output format conversion. Result shows that the optimization is technology independent and thus should suit well for not only FPGA implementation but also ASIC. This design can complete a standard 1 024 bit RSA encrypt operation with only 9 836 clock cycles. Compared to the recently proposed design in the literature, the proposed design can achieve an increase of over 50% in throughput.