基于可编程电路的低延时中值求取方法

针对高性能实时计算对中值求取等常用处理方法低延时性能要求越来越高,而当前利用FPGA等可编程电路实现中值求取存在流水延时较高且控制逻辑复杂的问题,提出一种基于可编程电路的低延时中值求取方法。利用FPGA等可编程电路丰富的逻辑运算和存储单元,可快速实现移位、截取、拼接及构建查找表,减少加减乘除等运算的特点,设计一种充分发挥其并行计算能力的中值求取方法,有效提升处理效率和减少流水延时。实验结果表明,中值求取流水延时最低可做到2个时钟周期,控制流程简单可行,硬件资源占用适当,并可推广到更大规模的数据序列中值求取运算中,符合高性能低延时计算领域的需求和趋势。

LOW DELAY MEDIAN SOLUTION METHOD BASED ON PROGRAMMABLE CIRCUIT

High performance real-time computing requires higher and higher performance of low delay in common processing methods such as median value getting. However, there are some problems in median value getting using FPGA, such as high pipeline delay and complex control logic. In order to solve this problem, this paper presented a low delay median solution based on programmable circuit. Using the rich logic operation and memory unit of programmable circuits such as FPGA, it was easy to realize the operation of shift, interception, splicing and construction of lookup table quickly, and reduce the operation of addition, subtraction, multiplication and division. We designed a median solution method to give full play to its parallel computing ability, which could effectively improve processing efficiency and reduce processing delay. The experimental results show that the median value time delay can be achieved 2 clock cycles, the control flow is simple and feasible, and the hardware resources are appropriately occupied. It can be extended to larger-scale data sequence median computation, which meets the needs and trends of high-performance and low-latency computing.