基于FPGA的变M/T归一化测速算法研究

针对永磁同步电机的测速问题,提出关于增量编码器的变M/T归一化测速算法,并基于Xilinx FPGA板级系统完成算法设计与实现。通过分析M/T算法在低速范围的局限性,添加速度预测单元实时指导计数脉冲个数选取。为便于算法移植,在算法中引入归一化的设计思想。针对算法中使用较多的乘法器,引入Booth算法降低整体算法设计对FPGA片内DSP的依赖性。仿真结果表明,基于FPGA的变M/T归一化测速算法转速测量误差在±0.4 r/min内,测速响应时间不超过3 ms。

A MODIFIED M/T NORMALIZED VELOCITY MEASUREMENT ALGORITHM BASED ON FPGA

Aiming at the problem of speed measurement of permanent magnet synchronous motor, this paper presented a modified M/T normalized speed measurement algorithm for incremental encoder, and completed the design and implementation of the algorithm based on Xilinx FPGA board-level system. By analyzing the limitation of M/T algorithm in the low speed range, a speed prediction unit was added to guide the selection of counting pulses in real time. In order to facilitate the transplantation of the algorithm, the idea of normalization was introduced into the algorithm. Booth algorithm was introduced to reduce the dependence of the whole algorithm design on the on-chip DSP for the multiplier used in the algorithm. The simulation results show that the speed measurement error of the modified M/T normalized speed measurement algorithm based on FPGA is within ±0.4 rad/min and the response time is less than 3 ms.