首页 | 官方网站   微博 | 高级检索  
     

基于不同排序方法的快速霍夫曼编码硬件实现
引用本文:李宜珂,王旃.基于不同排序方法的快速霍夫曼编码硬件实现[J].计算机科学,2017,44(Z11):476-479, 509.
作者姓名:李宜珂  王旃
作者单位:浙江大学电气工程学院 杭州310007,浙江大学电气工程学院 杭州310007
摘    要:针对软件霍夫曼静态编码计算量大,而动态霍夫曼编码使得解码器同样复杂的缺点,提出了一种准动态霍夫曼硬件编码器。该编码器每次对一组数据序列进行静态编码,然后将编码并行输出,从而使得编码器具有较高的编码速度,而其延迟时间仅为一次编码过程的总时间。首先,为了充分利用硬件并行特性,分别使用动态排序和静态排序两种排序网络,以适应不同场合的编码需要。然后,使用数据流驱动的硬件二叉树构建和解析结构得到信源符号对应的霍夫曼编码。最后,将储存在FIFO中的输入数据查表并输出。设计结果表明,当使用Nexys4 DDR平台时,该编码器可以工作于100MHz以上的频率,同时具有吞吐高、延迟低、编码效率高和译码器简单的特性。

关 键 词:霍夫曼编码  硬件排序  硬件二叉树  现场可编程门阵列  先入先出

Hardware Implementation of Fast Huffman Coding Based on Different Sorting Methods
LI Yi-ke and WANG Zhan.Hardware Implementation of Fast Huffman Coding Based on Different Sorting Methods[J].Computer Science,2017,44(Z11):476-479, 509.
Authors:LI Yi-ke and WANG Zhan
Affiliation:College of Electrical Engineering,Zhejiang University,Hangzhou 310007,China and College of Electrical Engineering,Zhejiang University,Hangzhou 310007,China
Abstract:Aiming at the drawback of static software Huffman coding which has large computational complexity and the problem of dynamic Huffman coding that makes the decoder more complicated,a quasi-dynamic hardware Huffman encoder was designed.This encoder encodes an array of data statically,then outputs the result parallelly which guarantees that it has a high encoding speed,and its dalay time is only the total time of an encoding process.First,for taking advantage of parallelism of hardware,static and dynamic sorting network are both implemented to meet different encoding demands.Then,a hardware binary tree building unit and a resolving unit driven by data flow are implemented to get the final Huffman codes.Finally,the Huffman codes are outputted based on data stored in FIFO.The design results illustrate that,this quasi-dynamic based on Nexys4 platform shows advantages of high working frequency (over 100MHz),high throughput,low latency and can simplify the design of decoder.
Keywords:Huffman coding  Hardware sorting  Hardware binary tree  Field-programmable gate array(FPGA)  First in first out(FIFO)
点击此处可从《计算机科学》浏览原始摘要信息
点击此处可从《计算机科学》下载全文
设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司    京ICP备09084417号-23

京公网安备 11010802026262号