超标量TURB052嵌入式微处理器结构设计

介绍了TURBO52的研究背景及技术路线,在保持对经典8051指令集后向兼容的前题下,通过重新进行结构设计来提高系统性能。介绍了指令流水线的结构设计,包括两路超标量结构、分支预测、动态执行和存储管理。在FPGA上运行真实控制系统应用程序测试表明,在相同工作频率下运行一系列系统软件可达经典8051的30倍以上,最高指令吞吐率每时钟周期两条指令。但由于未实现三级存储体系和数据高速缓存,工作在100 MHz以上性能的提升会受限。

Architecture design of superscalar embedded TURB052 microprocessor

In this paper, it is firstly give the background and the considerations to follow this technological roadmap of design the TURBO52. It then introduces the architecture design of instruction double issue super scalar pipeline, including the double-issue superscalar, branch prediction, dynamical execution and memory management. The various test patterns in running real applications indicates that ,under the same work clock frequency, the TURBO52 outperforms over 30 times faster than its traditional counterpart. However, owing to no implementation of data-cache and the three-layer-memory-hierarchy, the performance over 100 MHz is supposed to be hampered.