| 基于NiosⅡ的视频采集与DVI成像研究及实现 |
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| 引用本文： | 蔡欣荣,许泰峰,奚冠巍.基于NiosⅡ的视频采集与DVI成像研究及实现[J].电子技术应用,2010,36(4). |
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| 作者姓名： | 蔡欣荣 许泰峰 奚冠巍 |
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| 作者单位： | 中国船舶重工集团公司江苏自动化研究所,江苏,连云港,222006 |
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| 摘 要： | 采用FPGA作为视频采集控制和图像处理芯片,配置NiosⅡ软核,在FPGA片内完成图像处理和图像显示控制,简化了硬件电路和软件程序的设计。在FPGA片内编写视频采集时序,并配置NiosⅡ控制软核,模拟视频数据经视频解码芯片输出ITU-RBT.656格式数据送入FPGA,通过时序控制和NiosⅡ软核把视频解码数据依序存储在SSRAM中,并进行裁剪、交织、颜色处理。
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| 关 键 词： | 图像采集 FPGA NiosⅡ软核 ITU-RBT.656 DVI |
Research and realization of video capture based on NiosⅡ and DVI imaging |
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| CAI Xin Rong,XU Tai Feng,XI Guan Wei.Research and realization of video capture based on NiosⅡ and DVI imaging[J].Application of Electronic Technique,2010,36(4). |
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| Authors: | CAI Xin Rong XU Tai Feng XI Guan Wei |
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| Affiliation: | CAI Xin Rong,XU Tai Feng,XI Guan Wei (JiangSu Automation Research Institute of CSIC,Lianyungang 222006,China) |
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| Abstract: | This paper takes FPGA as video capture control and image processing chip,configure NiosⅡprocessor,processing image in FPGA,that simplify hardware circuit design and software design.Designing control program and burning it into FPGA, configuring NiosⅡprocessor,analog video signal captured by video decode chip and output the ITU-RBT.656 data sequence,the data sequence is captured by FPGA,through time scheduling and NiosⅡprocessor control,put the decoded data sequence into SS-RAM, and take image cut out,interlace and color process and so on. |
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| Keywords: | FPGA ITU-RBT 656 DVI |
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