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网络处理器体系结构分析
引用本文:李秋江,韦卫,贺志强.网络处理器体系结构分析[J].计算机工程与应用,2004,40(5):135-138.
作者姓名:李秋江  韦卫  贺志强
作者单位:1. 中国科学院计算技术研究所,北京,100080;中国科学院研究生院,北京,100039
2. 中国科学院计算技术研究所,北京,100080;联想研究院,北京,100085
基金项目:国家863高技术研究发展计划基金(编号:2002AA142030)
摘    要:该文旨在分析网络处理器能够同时满足高性能和灵活性要求的体系结构。而传统的网络设备单纯采用专用芯片或者基于RISC的通用处理器(GPPs),很难兼顾这两者要求。该文根据网络处理器的处理空间,将其映射为5个逻辑模块,这些模块由网络处理器中各个功能部件实现。然后分析了网络处理器的SMP和Pipeline两种并行结构,并进一步分析了隐藏延迟等实现加速的技术。最后分析了网络应用发展变化对网络处理器体系结构设计的挑战,并提出了解决办法。

关 键 词:网络处理器  体系结构  并行处理  隐藏延迟  网络应用
文章编号:1002-8331-(2004)05-0135-04

Analysis on the Architecture of Network Processors
Li Qiujiang , Wei Wei , He Zhiqiang.Analysis on the Architecture of Network Processors[J].Computer Engineering and Applications,2004,40(5):135-138.
Authors:Li Qiujiang  Wei Wei  He Zhiqiang
Affiliation:Li Qiujiang 1,2 Wei Wei 1,3 He Zhiqiang 1,31
Abstract:Th is paper aims at analyzing the architecture of network processors which can ser ve both high performance and flexibility purposes.while traditional network dev ices which consists purely of ASICs or RISC-based GPPs (General Purpose Proce ssors)could hardly satisfy both of the purposes.In this paper,we briefly des cribe the processing spaces of network processors,and mapping them into five lo gical blocks which are implemented by various function blocks of a practical net work processor.Then,we analyse the two kinds of Micro-architecture of netw ork processors:SMP and Pipeline parallel architecture,further more,we make a deep insight into some acceleration technologies,such as hide-latency.Con sequently,we list some challenges faced in the field of network processor arc hitecture design and find some solutions to these challenges.
Keywords:networ k processor  architecture  parallel processing  hide latency  network applicatio n  
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