基于FPGA器件的高速以太网入侵检测系统设计与实现

本文设计并实现了一种基于FPGA芯片的G比特以太网入侵检测系统。该系统将以太网数据帧头部和数据帧负荷相分离。首先利用Xilinx公司的XC2V1000型FPGA芯片实现数据帧头部的匹配；然后利用操作系统核心态模块实现数据帧负荷的匹配。从而将操作系统计算量降至最低．极大地提高了入侵检测系统整体性能实验数据证明．该系统可有效实现对高速以太网中多种攻击的检测与响应。

Design and Implementation of High-Performance Intrusion Detection System Based on FPGA Device for High-speed Ethernet

This paper proposes and implements a intrusion detection system for high-speed Ethernet. The system's whole pattern matching task is divided into two phases: packet header matching and packet payload matching. Firstly, It uses the Xilinx XC2V1000 FPGA device to implement the packet header matching; Secondly, It uses the kernel module of operation software to realize packet payload matching. The computation cost for packet matching is reduced to the minimum and the system performance is promoted highly. Experiment results demonstrate that this new intrusion detection system is effective to detect and respond attacks on the high-speed Ethernet.