LDPC码的多路并行编码器实现

针对空间数据系统咨询委员会(CCSDS)标准下低密度奇偶校验(LDPC)码编码器低硬件实现复杂度的应用需求,提出一种适用于不同码长、码率LDPC码的多路并行编码器实现架构。该架构通过重复利用编码器中的存储单元,将矩阵信息共享到所有并行的运算单元中从而提高资源利用率。进一步,在现场可编程门阵列(FPGA)平台上验证并测试码率分别为1/2、2/3及4/5的单路和多路编码器,测试结果表明采用多路并行架构的编码器吞吐量比单路编码器有明显的提高且均达到1 Gbps以上;与达到基本相同吞吐量的单路多组编码器相比,其查找表资源分别减少40%、44%和46%。该架构充分利用FPGA的存储资源进而有效降低硬件实现复杂度。

Implementation of multi-channel parallel encoder for LDPC codes

For the low implementation complexity requirement of the low-density parity-check ( LDPC) encoders in consultative committee for space data systems (CCSDS) standard, an implementation architecture of multi-channel parallel encoder is proposed for LDPC codes with different code lengths and code rates. The matrix information can be shared among all parallel computing units to improve resource utilization by repeatedly utilizing the storage unit in the encoder. Furthermore, the single-channel and multi-channel encoders with code rates of 1 / 2, 2 / 3 and 4 / 5 are verified and tested on the field programmable gate array (FPGA) hardware platform. The test results show that the throughput of the encoders adopting the multi-channel parallel coding scheme is higher than that of the single-channel encoders and achieves more than 1Gbps. The resources of the look-up table for the multi-channel encoders are reduced by 40%, 44% and 46%, respectively, compared with the single-channel encoders with multiple groups that achieves approximately the same throughput. By making full use of the storage resources in FPGA, this architecture can reduce the complexity of hardware implementation effectively.