| 基于FPGA的三模冗余UART电路设计 |
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| 引用本文： | 韩月涛,潘伟萍,杨帆,崔嵬.基于FPGA的三模冗余UART电路设计[J].电子测量技术,2011,34(3):57-61. |
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| 作者姓名： | 韩月涛 潘伟萍 杨帆 崔嵬 |
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| 作者单位： | 北京理工大学信息与电子学院; |
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| 摘 要： | 针对在星载复杂空间环境下UART(universal asynchronous receiver/transmitter)电路有可能发生单粒子翻转导致通信失效的问题,研究了基于反熔丝型FPGA的三模冗余UART电路设计方法.根据UART异步串行收发电路的功能特点,提出了采用反熔丝型的FPGA,将电路的核心功能嵌入到FP...
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| 关 键 词： | 三模冗余 反熔丝 通用异步串行通信(UART) 现场可编程门阵列(FPGA) |
UART circuit design with TMR based on FPGA |
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| Han Yuetao,Pan Weiping,Yang Fan,Cui Wei.UART circuit design with TMR based on FPGA[J].Electronic Measurement Technology,2011,34(3):57-61. |
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| Authors: | Han Yuetao Pan Weiping Yang Fan Cui Wei |
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| Affiliation: | Han Yuetao Pan Weiping Yang Fan Cui Wei (School of Information and Electronic,Beijing Institute of Technology,Beijing 100081) |
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| Abstract: | In the complex space environment of onboard system,SEU(Single Event Upset) may occur in UART(Universal Asynchronous Receiver Transmitter) circuit,which may lead the communication to failure.To address this issue,presents a TMR UART circuit design based on anti-fuse FPGA.Based on the features of UART asynchronous serial transceiver circuit,the asynchronous/serial port transceiver circuit TMR design which embedded into the anti-fuse FPGA and programmed in VHDL language is proposes in this paper.The working pr... |
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| Keywords: | triple module redundancy anti-fuse universal asynchronous receiver/transmitter field programmable gate array |
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