非零速启停的低功耗步进电机控制器研究

为了优化步进电机开环控制性能，对非零速启停的加减速曲线算法及其低功耗硬件逻辑实现进行了研究。针对零速启停的加减速曲线存在控制性能难以充分发挥的问题，提出了一种非零速启停的步进电机线性加减速曲线算法，将加减速过程划分为四种转动模式，可构建任意的线性速度剖面。首先理论推导了四种加减速转动模式的控制脉冲周期；其次结合流水线设计思想优化加减速曲线算法的硬件逻辑模型，在FPGA中设计了步进电机控制器IP核，并采用门控时钟等低功耗IC设计技术实现了IP核的低功耗；最后，搭建了实验平台进行验证。实验结果表明，IP核可以实现四种转动模式的非零速启停控制，实现了高实时、高精度驱动，提升了20%的控制性能，电路面积优化约30%，功耗降低53%，验证了方案的可行性与有效性。

The study on design of a Non-Zero Speed Start-Stop and low-power stepper motor controller

This study presents a design of a non-zero speed start-stop and low-power stepper motor controller. To achieve such design, the acceleration-deceleration curve algorithm for the realization of non-zero speed start-stop, and the hardware-logic design for the realization of low-power dissipation, have been proposed to improve the performance of the stepper motor open-loop control method. The acceleration-deceleration curve algorithm is able to divide the stepper motor rotation process to 4 different modes so that to establish any desired linear motor velocity profile, to tackle the problem of achieving the performance of non-zero speed start-stop. In this paper, the control pulse periods of the 4 different linear acceleration-deceleration process are theoretically derived; Then the hardware-logic model of the acceleration-deceleration process is optimized with the assistane of the Pipeline Design concept. The IP core of the stepper motor controller is built on a Field Programmable Gate Array (FPGA) , and ultilize the low-power ICs (e.g., Clock-Gating Technique) to achieve the low-power performance of the controller. Finally, an experimental platform is setup to demonstrate that, the IP core on FPGA is capable for the non-zero speed start-stop with 4 modes, and is able to drive the motor timely and precisely. The empirical results with statistical analysis show the proposed design is feasible and efficient, and successfully achieve 20% better control performance, 30% less electronic system circuit area, and 53% less power dissipation.