Challenges for Integration of Embedded FeRAMs in the sub-180 nm Regime

Ferroelectric memories (FeRAMs) are more and more using stack cells in 1T1C configuration. While none of these are already in real production, a great progress has been made when comparing these with strapped cells in 2T2C configuration. However the FeRAM community must be ready to face another challenging step in the evolution, i.e. the transition from planar to 3D capacitors. There's no consensus on the best approach to address this issue, which is probably a must at the 130 nm node. This paper reviews the limitations of the most popular approaches, then starts comparing two possible 3D FeCap structures (pin and cup-shaped). The final sections are dedicated to the introduction of a different strategy, trying to use a evolutionary approach. This is pursued starting with the development of a “quasi planar” FeCap in 0.35 μm technology that can evolve into a “quasi 3D” one at 0.18 μm node, and in a true one for 0.13 μm (or finer) rules.