基于DVB-S2标准低密度奇偶校验码译码器设计

为解决DVB—s2标准下码长较长，译码器资源消耗较高，但速率要求较高的问题，研究了DVB-S2标准LDPC（LowDensityParityCheckCode）码译码器的硬件结构。利用校验矩阵周期特性，以16200bit码长和0．6码率为例，设计了基于共享内存和后验概率累加储存的译码器结构。实验表明，该设计的LDPC码译码器共消耗24004个逻辑单元，6437个寄存器和448594bit的RAM，吞吐率达到289Mbit／s，不仅吞吐量大，而且寄存器和内存资源的消耗也小。

Design and Implementation of LDPC Decoder for DVB-S2

The hardware architecture of the DVB-S2 LDPC （Low Density Parity Check Code） code decoder is researched. According to the cyclical feature of the check matrix we have realized a decoder of the DVB-S2 LD- PC code whose rate is 3/5 and length is 16 200 bit. Experiment result shows that the total consumption of the LDPC decoder are 24 004 logic cells, 6 437 registers and 448 594 bits of RAM. And the throughput of is up to 289 Mbit/s. The structure of decoder using shared memory banks and writing the LLR （ Log-Likelihood Ratio） back to the RAM has low area and high throughput.