基于FPGA的基-4 FFT算法的硬件实现

针对高速数字信号处理的要求,提出用FPGA实现基-4FFT算法,并对其整体结构、蝶形单元进行了分析.采用蝶算单元输入并行结构和同址运算,能同时提供蝶形运算所需的4个操作数,具有最大的数据并行性,能提高处理速度;按照旋转因子存放规则,蝶形运算所需的3个旋转因子地址相同,且寻址方式简单;输出采取与输入相似的存储器;运算单元同时采用3个乘法的复数运算算法来实现.

Hardware Implementation of Radix 4 FFT Algorithm Based on FPGA

In accordance with the requirements of high speed digital signal processing,the algorithm of radix-4 implemented with FPGA and the integrated architecture and butterfly unit are analyzed.With butterfly unit input which is designed by parallel structure and the same address calculation,four operation codes the butterfly unit needs can be provided simultaneously to have the most data parallel and improve the speed of calculation.According to the rotation parameters memory regulation,the addresses of three rotation parameters of butterfly unit are the same with simple style of address generation and similar input and output memories.The operating unit adopted is implemented by three complex calculation algorithm of multiplication simultaneously.