亚45 nm技术节点平面式硅基CMOS电路制作的材料选择

随着45nm技术的临近，减小单个晶体管尺寸以提高晶体管集成度的方法逐渐达到物理极限。传统掺杂多晶硅，二氧化硅栅结构因硼杂质扩散穿透、多晶硅耗尽和电子隧穿等效应使深亚微米器件的性能退化。此外，沟道载流子迁移率退化也阻碍Si基MOS性能的提升。因此，需采用高k介质、金属栅和应变硅等新材料、新技术以改善Si基MOS管性能。本文在介绍这3种新材料优势的同时，分析了适合未来平面式硅基CMOS技术中的高介电常数材料和金属栅材料的种类，指出了未来电路中新材料的进一步发展方向。

Materials Used in Sub-45 nm Node Planar CMOS Technology

As the 45 nm nears, the dimension of a single transistor approaches the limits of physics. The traditional poly Si/Si02 gate stack structures will not continue to be used to MOS device owing to boron atoms penetrating through the gate oxide, the depletion of poly Si and direct tunnel current leakage. Additionally, the degradation of carrier mobility also has disadvantage to the further development of the scaled Si based MOS devices. Therefore, novel materials such as high k dielectrics, metal gate and strained Si material will be utilized in 45 nm node and beyond. This article reviews the current status of high k dielectrics, metal gate and strained Si materials for microelectronics. Meantime, the prospect of the three materials in advanced scaled microelectronic devices is also introduced. The combination of these three materials with other new technology into a chip will be effective planar CMOS circuit.