Timing driven floorplanning for general cells |
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Authors: | Qi X Feng Z Yan X |
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Affiliation: | JCCAD Res. Center, Hangzhou Inst. of Electr. Eng. ; |
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Abstract: | The idea of timing driven floorplanning is presented. While optimising the interconnection (wire) delay between cells using the weighted min-cut method, the authors used the nonlinear programming method to reduce both the cell and interconnection delays in the critical paths. Experiments on the examples produced promising results, indicating that the method is effective at optimising the layout phase in VLSI design |
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