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High performance VLSI architecture for division and square root |
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| Authors: | McQuillan SE McCanny JV Woods RF |
| Affiliation: | Inst. of Adv. Microelectro., Queens Univ. of Belfast, UK; |
| Abstract: | A novel high performance bit parallel architecture to perform square root and division is proposed. Relevant VLSI design issues have been addressed. By employing redundant arithmetic and a semisystolic schedule, the throughput has been made independent of the size of the array.< |
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