| 深亚微米VLSI电路中互连线的几何优化设计 |
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| 引用本文： | 宋任儒,阮刚,肖夏,Thomas Otto,Thomas Gessner.深亚微米VLSI电路中互连线的几何优化设计[J].固体电子学研究与进展,2000,20(1):84-93. |
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| 作者姓名： | 宋任儒 阮刚 肖夏 Thomas Otto Thomas Gessner |
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| 作者单位： | 复旦大学电子工程系!专用集成电路与系统国家重点实验室，上海，200433，复旦大学电子工程系!专用集成电路与系统国家重点实验室，上海，200433，Chemnitz技术大学微工艺中心!德国，Chemnitz技术大学微工艺中心!德国，Chemnitz技术大学微工艺中心!德国，Chemnitz技术大学微工艺中心!德国 |
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| 摘 要： | 基于三维 L aplace方程的 Silvaco Interconnect3D模拟程序数值解 ,对互连寄生电容进行了计算 ,其结果用于 0 .2 5μm CMOS技术互连延迟及串扰的 SPICE模拟中。模拟结果表明 ,基于W/ P=0 .3～ 0 .4的布线准则可以获得最优的互连延迟与串扰 (Crosstalk)特性 ,通过优化互连线及驱动管的几何尺寸可以显著地减小互连线的延迟及串扰噪声。
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| 关 键 词： | 深亚微米超大规模集成电路 互连延迟 串扰 |
Geometrical Optimizing Design of Interconnection for Deep Sub micrometer VLSI Circuits |
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| Song,Renru,Ruan,Gang.Geometrical Optimizing Design of Interconnection for Deep Sub micrometer VLSI Circuits[J].Research & Progress of Solid State Electronics,2000,20(1):84-93. |
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| Authors: | Song Renru Ruan Gang |
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| Abstract: | Based on the 3 D numerical solution of Laplace equation with a Silvaco Interconnect 3D simulator, the parasitic capacitances of interconnection have been extracted, with the results used in the SPICE simulation of interconnection delay and crosstalk for 0.25 μm CMOS technique. The simulated results show that the optimizing characteristics of interconnection delay and crosstalk can be approached with W/P=0.3～0.4, the amplitude of interconnection delay and crosstalk noise can be considerably minimized by optimally selecting the geometrical sizes of interconnection line and the driver. |
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| Keywords: | deep sub micrometer VLSI interconnection delay crosstalk |
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