近阈值电压下可容错的末级缓存结构设计

近阈值电压技术通过降低晶体管的电源电压来降低芯片能耗和提升能效。但是，近阈值电压技术会在Cache中引起大量位错误，严重影响末级缓存的功能。针对近阈值电压下超过1%的位错误率造成的Cache故障问题，该文提出一种基于传统6T SRAM单元的可容错的末级缓存结构(FTLLC)。该策略对缓存条目中的错误进行了低错纠正和多错压缩，提高了Cache中数据保存的可靠性。为了验证FTLLC的有效性，该文在gem5中实现了该结构，并运行了SPEC CPU2006测试集进行仿真实验。结果表明，对于650 mV电压下65 nm工艺的末级缓存，FTLLC与Concertina压缩机制相比在4-Byte粒度下末级缓存可用容量增加了24.9%，性能提高了7.2%，末级缓存的访存缺失率下降了58.2%，而面积和能耗开销仅有少量增加。

Fault-tolerant Last Level Cache Architecture Design at Near-threshold Voltage

Near-threshold voltage computing enables transistor voltage scaling to continue with Moore’s Law projection and dramatically improves power and energy efficiency. However, a great number of bit-cell errors occur in large SRAM structures, such as Last-Level Cache (LLC). A Fault-Tolerant LLC (FTLLC) design with conventional 6T SRAM cells is proposed to deal with a higher failure rate which is more than 1% at near-threshold voltage. FTLLC improves the reliability of data stored in Cache by correcting the single-error and compressing multi-errors in Cache entry. To validate the efficiency of FTLLC, FTLLC and prior works are implemented in gem5, and are simulated with SPEC CPU2006. The experiment shows that compared with Concertina at 650 mV, the performance of a 65 nm FTLLC with 4-Byte subblock size improves by 7.2% and the Cache capacity increases by 24.9%. Besides, the miss rate decreases by 58.2%, and there are little increases on area overhead and power consumption.