一种高动态双模抗干扰接收机设计方法

针对抗干扰多阵元前端低功耗制约抗干扰能力的问题,为了减小功耗的同时提升抗干扰能力,提出一种新颖的BDII/GPS双通道4阵元抗干扰接收前端,在低噪声放大器中实现了一种三端口的双通带电路,具有小于0.1 dB的插损以及30 dB以上的隔离度。采用了一种频率流程设计方法,结合仿真选取频率从而减小了机内的组合干扰,同时简化了中频滤波器的种类;采用了无源混频与中频放大的下变频方案,提高通道线性度(IIP3)的同时降低功耗、优化通道噪声系数(NF),研究了采样钟fclk远端相位噪声折叠的效应,设计了一种窄带相位噪声滤波器,提高了中频采样的信噪比。该接收机包含一种形式简单的电源及晶振切换电路。测试结果表明,接收机同时实现了42 dB固定增益,4.37 W低功耗,超过29 dBm的OIP3线性度以及优于80 dB的抗三干扰能力。

A Design Method of High Dynamic Dual-mode Anti-jamming Receiver

Aiming at the current situation that low power consumption of anti-jamming multi-array elements restricts anti-jamming capability,in order to reduce power consumption and enhance anti-interference capability,this paper proposes a novel BDII/GPS dual-channel 4-element anti-jamming receiver front end.A three-port dual-pass circuit is implemented in a low noise amplifier,which has insertion loss of less than 0.1 dB and isolation of more than 30 dB.A frequency flow design method is adopted to reduce the combined interference and simplify the types of IF filters by choosing frequencies in combination with simulation.The scheme of passive mixing and IF amplification is adopted to improve the channel linearity(IIP3)while reducing power consumption and optimizing the channel noise factor(NF).A narrow-band phase noise filter is designed to improve the signal-to-noise ratio of IF sampling.The receiver contains a simple power source and crystal switching circuit.The test results show that the receiver can achieve the fixed gain of 42 dB fixed gain,low power consumption of 4.37 W,OIP3 linearity of more than 29 dBm and anti-jamming capability more than 80 dB.