一种低抖动电荷泵锁相环频率合成器

设计一种低抖动电荷泵锁相环频率合成器,输出频率为400 MHz~1 GHz。电路采用电流型电荷泵自举结构消除电荷共享效应,同时实现可编程多种输出电流值。通过具体的频率范围来选择使用的VCO,获得更小的锁相环相位抖动。电路采用0.13μm 1.2 V CMOS工艺,芯片面积为0.6 mm×0.5 mm。Hsim后仿真结果显示当输出频率为1 GHz时,锁相环频率合成器的锁定时间为4.5μs,功耗为19.6 mW,最大周对周抖动为11 ps。

A Low-jitter Charge-pump Phase-locked Loop Synthesizer

A low-jitter charge pump phase-locked loop synthesizer with output frequency from 400 MHz to 1 GHz is designed. Charge sharing effect is eliminated by bootstrapping of current-steering charge pump, which can output multiple currents by programming. The VCO is chosen according to the specific frequency range to obtain lower jitter in PLL. The circuit is implemented in 0.13 μm CMOS process and operates from 1.2 V supply. The chip area is about 0.6 mm×0.5 mm. The Hsim Post-Simulation results show that the locking time is 4.5 μs, the power is 19.6 mW, and the maximum cycle to cycle jitter is 11 ps, when output frequency reaches 1 GHz.