H.264编码器中1/4像素精度插值算法的VLSI实现

H.264视频编码标准中引入了1/4像素精度插值算法,大大提高了压缩效率,但同时使运算复杂度增加、存储带宽增大。针对以上问题,从运动估计的角度出发,采用一步插值法和数据复用技术,可使带宽减少26%,处理周期可减少45%;设计了相应的硬件结构:采用了5级流水线实现一步插值算法,通过输入缓冲单元实现了参考数据的复用;针对插值过程中产生的大量数据,采用乒乓操作结构,保证数据及时传递。该结构可以显著降低带宽,提高吞吐率,完全可以应用于实时编码器中。

A VLSI Architecture for Quarter-Pixel Interpolation in H.264/AVC Encoder

The new H.264/AVC coding standard adopts the quarter-pixel resolution interpolation algorithm and enhances the performance of compression.However,the technique increases the computation complexity and memory bandwidth in the implementation of H.264/AVC encoder.For these problems above,one step interpolation algorithm and a data reuse technique are presented in this paper from a motion estimation point of view,which can reduce memory bandwidth and computation complexity efficiently.An input buffer is introduced to implement data reuse.According to the principle of ping-pong,an output buffer is designed to transmit interpolated data promptly.Theoretical analysis shows that our architecture has some advantage both in low bandwidth and high throughput,and can be used in real-time encoder.