Patterning issues for the fabrication of sub-micron memory capacitors' electrodes

This paper describes some of the key issues associated with the patterning of metal electrodes of sub-micron (especially at the critical dimension (CD) of 0.15 μm) dynamic random access memory devices. Due to reactive ion etching lag, the Pt etch rate decreased drastically below the CD of 0.20 μm and thus K-th storage node electrode with the CD of 0.15 μm could not be fabricated using the Pt electrodes. Accordingly, we have proposed novel techniques to surmountly-the above difficulties. The Ru electrode cannot for the stack-type structure is introduced and alternative multischemes based on the introduction of the concave-type selfstructure upto using semi-Pt or Ru as an electrode material are outlined respectively.