Parameter variation aware hybrid TFET-CMOS based power gating technique with a temperature variation tolerant sleep mode |
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| Affiliation: | 1. Complutense University of Madrid, Computer Architecture and Automation, Facultad de Informática, c/Prof. García Santesmases s/n, 28040 Madrid, Madrid, Spain;2. Northwestern University of Evanston, Department of Electrical Engineering and Computer Science, Tech Building, L471, 2145 Sheridan Road, 60208 Evanston (IL), United States;1. Institut für Werkstoffe der Elektrotechnik II, RWTH Aachen University, Germany;2. Peter Grünberg Institut 7, Forschungszentrum Jülich GmbH, Jülich, Germany;3. Jara – Fundamentals for Future Information Technology, Jülich, Germany;1. Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi, New Delhi 110021, India;2. Department of Physics, Motilal Nehru College, University of Delhi, New Delhi 110021, India;3. Department of Electronics and Communication Engineering, Maharaja Agrasen Institute of Technology, Delhi 110086, India;1. State Key Laboratory of Coal Resources and Safe Mining, China University of Mining and Technology, Beijing 100083, China;2. School of Mechanical Electronic & Information Engineering, China University of Mining and Technology, Beijing 100083, China |
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| Abstract: | In this work, we discuss the origin and temperature dependence of various mechanisms behind the flow of leakage current in two topologies of TFET – basic TFET and pocket doped TFET. It is shown that the leakage current of pocket doped TFET shows relatively less variations with change in temperature when compared with MOSFET and basic TFET, and hence they can be deployed in low voltage temperature variation prone applications. But, this advantage of pocket-doped TFET is overshadowed by the huge sensitivity of its ON-state current towards variations in doping concentration at the tunnel junction. Hence, the fabrication of the TFET based circuits requires a negotiation with the yield and cost of the fabrication process. In order to mitigate this issue, we propose a hybrid TFET-CMOS based power gating technique. The hybrid technique utilizes a minimum number of TFETs to reduce the sleep mode leakage current, while enabling a temperature variation tolerant sleep mode at a supply voltage of 0.6 V. |
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| Keywords: | Tunnel FET (TFET) Leakage current Power gating Hybrid TFET-CMOS Temperature variation Parameter variation |
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