A Radix-4 New Svobota-Tung Divider with Constant Timing Complexity for Prescaling |
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Authors: | Jen-Shiun Chiang and Min-Shiou Tsai |
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Affiliation: | (1) Department of Electrical Engineering, Tamkang University, Tamsui, Taipei, Taiwan |
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Abstract: | A new floating-point division architecture that complies with the IEEE 754-1985 standard is proposed in this paper. This architecture is based on the New Svoboda-Tung (NST) division algorithm and the radix-4 MROR (maximally redundant maximally recoded) signed digit number system. In NST division, the divisor and dividend must be prescaled. We summarize a general systematic method to accomplish the prescaling, and we also propose a hardware scheme such that the timing complexity is constant regardless of the bit length of the divisor. For the divider implementation, a new MROR signed digit adder with carry free characteristic is proposed for addition and subtraction, and this adder can improve the cycle time significantly. A 32-b/32-b radix-4 divider is thus designed in Verilog HDL; the simulation results show that this architecture is implementable using currently available libraries. The hardware complexity and performance of this divider is competitive with conventional SRT dividers. |
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Keywords: | computer arithmetic floating-point division new Svoboda-Tung division prescaling radix-4 signed digit number system Svoboda-Tung division |
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