| 一种10位50MHz流水线模数转换器的设计 |
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| 引用本文： | 王林锋,周建伟,甘小伟,刘利宾,邢少川.一种10位50MHz流水线模数转换器的设计[J].半导体技术,2012,37(2):122-125. |
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| 作者姓名： | 王林锋 周建伟 甘小伟 刘利宾 邢少川 |
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| 作者单位： | 河北工业大学微电子研究所,天津,300130;河北工业大学微电子研究所,天津,300130;河北工业大学微电子研究所,天津,300130;河北工业大学微电子研究所,天津,300130;河北工业大学微电子研究所,天津,300130 |
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| 摘 要： | 采用每级1.5 bit和每级2.5 bit相结合的方法设计了一种10位50 MHz流水线模数转换器。通过采用自举开关和增益自举技术的折叠式共源共栅运算放大器,保证了采样保持电路和级电路的性能。该电路采用华润上华(CSMC)0.5μm 5 V CMOS工艺进行版图设计和流片验证,芯片面积为5.5 mm2。测试结果表明:该模数转换器在采样频率为50 MHz,输入信号频率为30 kHz时,信号加谐波失真比(SNDR)为56.5 dB,无杂散动态范围(SFDR)为73.9 dB。输入频率为20 MHz时,信号加谐波失真比为52.1 dB,无杂散动态范围为65.7 dB。
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| 关 键 词： | 流水线模数转换器 采样保持电路 运算放大器 自举开关 增益自举 |
Design of 10 Bit 50 MHz Pipelined A/D Converters |
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| Wang Linfeng
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Zhou Jianwei
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Gan Xiaowei
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Liu Libin
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Xing Shaochuan.Design of 10 Bit 50 MHz Pipelined A/D Converters[J].Semiconductor Technology,2012,37(2):122-125. |
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| Authors: | Wang Linfeng Zhou Jianwei Gan Xiaowei Liu Libin Xing Shaochuan |
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| Affiliation: | (Institute of Microelectronics Hebei University of Technology,Tianjin 300130,China) |
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| Abstract: | A 10 bit 50 MHz pipelined ADC was presented by using the architecture of 1.5 bit/stage and 2.5 bit/stage.The gain-boosting folded cascade operationd amplifier and bootstrap switch were used to guarantee the performance of the sample and hold circuit and the sub-stages.The ADC was fabricated in the CSMC 0.5 μm CMOS process under the 5 V voltage.The chip area is 5.5 mm2.The measured results indicate that the ADC exhibit 56.5 dB SNDR,73.9 dB SFDR for 30 kHz input frequency at 50 MHz and 52.1 dB SNDR,65.7 dB SFDR for 20 MHz input frequency at 50 MHz. |
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| Keywords: | pipelined ADC sample/hold circuit operational amplifier bootstrap switch gain-boosted |
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