| 高分辨率时间数字转换电路的PLD实现 |
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| 引用本文： | 王福源,杨玉叶,时伟,王玮.高分辨率时间数字转换电路的PLD实现[J].半导体技术,2006,31(6):452-455,466. |
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| 作者姓名： | 王福源 杨玉叶 时伟 王玮 |
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| 作者单位： | 郑州大学信息工程学院,郑州,450002;郑州大学信息工程学院,郑州,450002;郑州大学信息工程学院,郑州,450002;郑州大学信息工程学院,郑州,450002 |
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| 摘 要： | 高分辨率时间数字转换系统(TDC)采用环形延时门单元(RGDS)高分辨率系统,在可编程器件(PLD)上实现,解决了延时门的综合、延时时间的离散性等问题.由于设计、实现和集成电路工艺无关,所以可以方便地移植到其他系统和PLD芯片中.本设计在Altera公司的CPLD芯片上的仿真测试表明,时间分辨率最高可达3.5ns.本实验通过了时序仿真和硬件测试.
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| 关 键 词： | 时间数字转换 可编程逻辑器件 环形延时门单元 |
| 文章编号： | 1003-353X（2006）06-0452-04 |
| 收稿时间： | 2005-11-24 |
| 修稿时间： | 2005-11-24 |
PLD-Based Realization of High Resolution Time-to-Digit Converter |
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| WANG Fu-yuan,YANG Yu-ye,SHI Wei,WANG Wei.PLD-Based Realization of High Resolution Time-to-Digit Converter[J].Semiconductor Technology,2006,31(6):452-455,466. |
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| Authors: | WANG Fu-yuan YANG Yu-ye SHI Wei WANG Wei |
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| Affiliation: | College of Electrical, Zhengzhou University, Zhengzhou 450002, China |
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| Abstract: | The realization of a high resolution time-to-digital converter is given, the ring gate delay system (RGDS) was applied to realize the high resolution. It was based on the PLD chips. The design solved the problems like the synthesize of gate delay system, the identical gate delay time etc. The design has no relation with the manufacture techniques of IC, so it can be easily reused in other designs and PLD chips. The simulation and test results based on CPLD chips produced by Altera show that the highest resolution can reach 3.5ns. The hardware test shows that the design is successful. |
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| Keywords: | time digital converter(TDC) PLD ring gate delay system(RGDS) |
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