| 32位高速浮点乘法器优化设计 |
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| 引用本文： | 周德金,孙锋,于宗光.32位高速浮点乘法器优化设计[J].半导体技术,2007,32(10):871-874. |
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| 作者姓名： | 周德金 孙锋 于宗光 |
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| 作者单位： | 江南大学,信息工程学院,江苏,无锡,214036;中国电子科技集团公司,第五十八研究所,江苏,无锡,214035 |
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| 摘 要： | 设计了一种用于频率为200 MHz的32位浮点数字信号处理器(DSP)中的高速乘法器.采用修正Booth算法与Wallace压缩树结合结构完成Carry Sum形式的部分积压缩,再由超前进位加法器求得乘积.对乘法器中的4-2压缩器进行了优化设计,压缩单元完成部分积压缩的时间仅为1.47 ns,乘法器延迟时间为3.5 ns.
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| 关 键 词： | 浮点乘法器 Booth编码 4-2压缩器 超前进位加法器 |
| 文章编号： | 1003-353X（2007）10-0000-04 |
| 修稿时间： | 2007-04-20 |
Design of a 32-bit High-Speed Floating-Point Multiplier |
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| ZHOU De-jin,SUN Feng,YU Zong-guang.Design of a 32-bit High-Speed Floating-Point Multiplier[J].Semiconductor Technology,2007,32(10):871-874. |
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| Authors: | ZHOU De-jin SUN Feng YU Zong-guang |
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| Affiliation: | 1.Information Engineering Institute,Southern Yangtze University,Wuxi 214036,China;2.The 58th Research Institute,CETC,Wuxi 214035,China |
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| Abstract: | A high-speed multiplier in 200 MHz 32bit floating-point DSP was presented.Modified booth algorithm and the Wallace tree were used to reduce the carry save partial product to sum and carry vectors,a carry look-ahead adder was designed to convert the sum and carry vectors to final format.The operating cycle time of the compression unit is 1.47 ns by optimizing the 4-2 compressors,the operating cycle time of the multiplier is 3.5 ns. |
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| Keywords: | floating-point multiplier booth-encoding 4-2 compressor carry look-ahead adder(CLA) |
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