Using a WLFSR to Embed Test Pattern Pairs in Minimum Time |
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Authors: | Dimitri Kagaris Spyros Tragoudas |
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Affiliation: | (1) Electrical & Computer Engineering Department, Southern Illinois University, Carbondale, IL 62901, USA |
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Abstract: | We propose a methodology for reducing the number of test cycles needed by a Weighted LFSR (WLFSR) to reproduce a 2P × W test matrix T of P pattern pairs. The methodology introduces a very small number of extra cells into the WLFSR and uses appropriate combinational mapping logic in order to make the time be equal to that required by a (W + )-bit WLFSR to generate vectors containing the W bits of the first pattern for each pair plus the extra bits. We present an algorithm that makes the value of be less than or equal to log2, where is the size of the maximum subset of pairs in T with identical first patterns. This is a significant improvement over the time E
P,W · P required by a trivial approach that uses a WLFSR with W cells to generate the first patterns of the pairs and a P × W ROM to store the second patterns of the pairs. Experimental results on the application of the methodology to the embedding of test matrices for path delay faults are particularly encouraging, even for very large numbers of test pattern pairs that are necessary for provably high fault coverage. |
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Keywords: | built-in self-test weighted random LFSRs two-pattern test sets delay testing |
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