| 卷积编码及Viterbi解码的FPGA实现及应用 |
| |
| 引用本文： | 何金花,杨金功.卷积编码及Viterbi解码的FPGA实现及应用[J].现代电子技术,2013(23):30-32. |
| |
| 作者姓名： | 何金花 杨金功 |
| |
| 作者单位： | 陕西凌云电器集团有限公司,陕西宝鸡721006 |
| |
| 摘 要： | 卷积码在现代无线通信系统中应用十分广泛，Viterbi译码是最常用的一种对卷积码的译码算法。介绍了卷积编码及Viterbi串行解码的原理及其FPGA的实现。在保证系统性能的前提下讨论了分帧式编解码在实际系统中的应用。
|
| 关 键 词： | 卷积码 Viterbi译码 误码率 FPGA |
Implementation and appliancation of convolutional encoding and Viterbi decoding algorithm with FPGA |
| |
| HE Jin-hua,YANG Jin-gong.Implementation and appliancation of convolutional encoding and Viterbi decoding algorithm with FPGA[J].Modern Electronic Technique,2013(23):30-32. |
| |
| Authors: | HE Jin-hua YANG Jin-gong |
| |
| Affiliation: | (Shaanxl Lingyun Electronics Group Co., Ltd., Baoji 721006, China) |
| |
| Abstract: | Convolutional code has been widely used in modern wireless communication. Viterbi decoding is a common algo- rithm for convolutional code. The principle of convolutional encoding and Viterbi serial decoding are presented, along with the FPGA implementation. The application of coder and decoder by frame type in real system is discussed in the condition of good performance. |
| |
| Keywords: | convolutional code viterbi decode bit error rate FPGA |
| 本文献已被 维普 等数据库收录！ |
