| 基于混合架构的H.264/AVC视频编码器设计 |
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| 引用本文： | 张卫兵,李先华,石旭利,滕国伟,张兆扬.基于混合架构的H.264/AVC视频编码器设计[J].电视技术,2007,31(10):30-32. |
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| 作者姓名： | 张卫兵 李先华 石旭利 滕国伟 张兆扬 |
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| 作者单位： | 上海大学,通信与信息工程学院;新型显示技术及应用集成教育部重点实验室,上海,200072 |
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| 摘 要： | 提出了基于DSP FPGA混合平台的H.264/AVC编码器设计思路与实现方法.以DSP为主处理器,FPGA为协处理器实现算法的硬件加速,针对编码器中最复杂耗时的模块,设计相应的硬件加速引擎.并针对硬件加速引擎制定出便于控制和数据传输的软/硬件通信协议,实现了H.264/AVC D1编码器所需的实时性能.
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| 关 键 词： | 运动估计 接口协议 混合架构 视频编码器 |
| 文章编号： | 1002-8692（2007）10-0030-03 |
| 修稿时间： | 2007-07-09 |
Design of H.264/AVC Video Coder Based on Mixed Architecture |
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| ZHANG Wei-bing,LI Xian-hua,SHI Xu-li,TENG Guo-wei,ZHANG Zhao-yang.Design of H.264/AVC Video Coder Based on Mixed Architecture[J].Tv Engineering,2007,31(10):30-32. |
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| Authors: | ZHANG Wei-bing LI Xian-hua SHI Xu-li TENG Guo-wei ZHANG Zhao-yang |
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| Affiliation: | School of Communication and Information Engineering Shanghai University; Key Lab of Advanced Display and System Application, Ministry of Education, Shanghai 20072, China |
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| Abstract: | A design and implementation method of H.264/AVC encoder based on mixed structure is introduced, in which DSP is used as a main processor and FPGA as an assistant processor to accelerate arithmetic by hardware. In order to meet required real-time performance, hardware engine is designed for the most complicated and time-consuming module. According to the engine, it constitutes a software and hardware communication agreement, which makes control and data transporting easily, and realizes the real-time performances which H.264/AVC D1 coder needs. |
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| Keywords: | motion estimation interface protocol mixed architecture video coder |
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