一种低复杂度的Log-MAP译码器结构

根据实际中Turbo译码器硬件实现的重要性,提出了一种适合于并行计算的改进Log-MAP译码算法,即在其译码计算中间参数的过程中,将具有n个输入变量的最大近似算法max*运算简化为取最大值的max运算和相关函数的计算,减少了存储量,有效实现了低复杂度的Turbo译码器的硬件结构。将此改进的算法应用于CCSDS标准和Wi MAX标准中,仿真结果表明,所提出的简化的近似算法与传统的Log-MAP算法对比,有效降低了译码复杂度和时延,而且纠错性能接近Log-MAP算法,便于实际工程应用。

Low complexity Log-MAP decoder architecture

According to the importance of hardware implementation of Turbo decoder in practice, an improved Log-MAP decoding algorithm suitable for parallel calculation is proposed. In the decoding process of Turbo codes, when calculating the intermediate parameters, this new algorithm replaces the n-input max* operation with the max operation and correlation function calculation, it is effective in reducing the area of storage, and turbo decoder hardware architectures can be implemented with very low-complexity. The improved algorithm is applied in the CCSDS standard and Wi-MAX standard, the simulation results show that the proposed algorithm reduces the decoding complexity and time-delay, and the BER performance is approximate to Log-MAP algorithm, so it has certain feasibility in the practical application.