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Investigation on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-μm CMOS technology |
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| Authors: | Shih-Hung Chen Ming-Dou Ker |
| Affiliation: | a Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung University, 1001 Ta-Hsueh Road, Hsinchu, Taiwan b Circuit Design Department, SoC Technology Center, Industrial Technology Research Institute, Hsinchu, Taiwan c Department of Electronic Engineering, I-Shou University, Kaohsiung, Taiwan |
| Abstract: | NMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the desired ESD protection capability. All of them are usually based on a similar circuit scheme with multiple-stage inverters to drive the main ESD clamp NMOS transistor with large device dimension. In this work, the designs with 3-stage inverter and 1-stage inverter controlling circuits have been studied to verify the optimal circuit schemes in the NMOS-based power-rail ESD clamp circuits. Besides, the circuit performances among the main ESD clamp NMOS transistors drawn in different layout styles cooperated with the controlling circuit of 3-stage inverters or 1-stage inverter are compared. Among the NMOS-based power-rail ESD clamp circuits, an abnormal latch-on event has been observed under the EFT test and fast power-on condition. The root cause of this latch-on failure mechanism has been clearly explained by the emission microscope with InGaAs FPA detector. |
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