| Abstract: | In this paper, we present the functionality fault model and demonstrate its feasibility and advantages. In current designs, the fan-in of the modules implemented in CMOS standard cell, mask programmable or field-programmable gate array technologies rarely exceeds 4 on average. A functionality fault model, based on the complete enumeration of the truth table of each logic module, is thus entirely feasible and enhances the quality of the test significantly. Tests based on this model provide complete coverage of module behavior and interior faults as well as input stuck-at and bridging faults of any multiplicity, reducing the need for technology and implementation-specific fault models. We have implemented the prototype software test-dc and demonstrated its application to generate high-quality test patterns. |
